DAP USB 3.0 Port <N> Control 1 (DAP_ESS_PORT_CONTROL_1_REG_0_MMIO) – Offset 8ac8 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

DAP USB 3.0 Port <N> Control 1 (DAP_ESS_PORT_CONTROL_1_REG_0_MMIO) – Offset 8ac8

Control and status registers for all DRD eSS links.
All bits in this register must be in the Always ON Power domain (un-gated SUS or AON as appropriate).
The register applies to individual port. The offset of each port: 0x8AC8 + N*0x10.
For example:
Port 0 offset: 0x8AC8
Port 1 offset: 0x8AD8
Port 2 offset: 0x8AE8
...

Bit Range	Default	Access	Field Name and Description
31:11	0h	RO	Reserved
10:8	1h	RO	Connector Type (CONNECTOR_TYPE) Specifies type of connector associated with this port. 000: Type C (default) 010: Type A. Others: reserved. Default of this field may be over-written by soft-strap. SW may program this field to make HW operation in response to the programmed connector type that can be different from the actual physical connector type.
7:5	0h	RO	Reserved
4	1h	RW	Fast Rx Termination Switch Disable (FRTSD) This field enables propagation of xHCI Rx termination to MODPHY Rx termination upon detection of host subscription event instead of based on HOST operation state. This is to hide the switching latency in case the switching latency results in external super-speed capable USB device falling into USB2 mode. The fall into USB2 mode can happen when the external USB device fails to timely detect the USB host in super speed mode thanks to absence of USB host Rx termination within some USB specification constrained time limit. 0: Enables propagation of xHCI Rx termination to MODPHY Rx termination upon detection of host subscription event, or xDCI Rx termination device subscription event. MODPHY Rx termination is driven to 0 otherwise. 1: Enables propagation of xHCI Rx termination to MODPHY Rx termination based on HOST operation state. Enables propagation of xDCI Rx termination to MODPHY Rx termination when xDCI samples utmisrp_bvalid at 1. MODPHY Rx termination is driven to 0 otherwise.
3	1h	RW	Rx Termination Control Override (RTCO) This field specifies how MODPHY Rx termination is controlled in DISCONN state as defined in DAP operation states. 0: xHCI Rx termination is propagated to MODPHY Rx termination in DISCONN state. 1: Neither xHCI nor xDCI Rx termination is propagated to MODPHY Rx termination in DISCONN state. Instead, DAP HW disables MODPHY Rx termination in DISCONN state.
2	0h	RW	USB3 SNPS PHY Wake Wire Assert (USB3 Wake Wire Assert) USB3 Wake Wire Assert 1: Wake Wire is asserted always 0: Wake wire is controlled by PG control logic
1	0h	RW	HW VBus Enable (HW_VBUS_ENABLE) This field applies to Port 0 (0-based) only. HW default value is parameterized. HW loads this field upon availability of switch mode soft-strap. SW may program this field. If set to 1, HW VBus IO pin is used to directly control VBus indication to xDCI. If cleared to 0, SW VBus field is used to directly control VBus indication to xDCI. Any other port behaves as if this field were 0.
0	0h	RW	HW ID Enable (HW_ID_ENABLE) This field applies to Port 0 (0-based) only. HW default value is parameterized. HW loads this field upon availability of switch mode soft-strap. SW may program this field. If set to 1, HW ID IO pin is used to directly control switch. If cleared to 0, connector event field is used to directly control switch except for Express Card in HW mode. Express Card may dynamically operate in HW mode if the relevant wire-based interface is active. Any other port behaves as if this field were 0.