DAP USB 3.0 Port <N> Status (DAP_ESS_PORT_STATUS_REG_0_MMIO) – Offset 8acc - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Introduction
CNVi WiFi* PCI Configuration
eSPI PCI Configuration
eSPI PCR
GPIO Commumity 0
GPIO Commumity 1
GPIO Commumity 2
GPIO Commumity 3
GPIO Commumity 4
GPIO Commumity 5
GSPI Additional MMIO
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- AHCI Index Register (INDEX)
- AHCI Data Register (DATA)
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- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
- MSI-X Pending Bit Array QW 1 (MXPQW0_DW1)
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SATA Port 0 ABAR
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SATA Port 2 ABAR
SATA Port 3 ABAR
SATA Port 4 ABAR
SATA Port 5 ABAR
SATA Port 6 ABAR
SATA Port 7 ABAR
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SMBus PCI Configuration
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SPI PCI Configuration
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- Device Idle Control Register (THC_M_CMN_DEVIDLECTRL)
- THC LTR Control Register (THC_M_CMN_LTR_CTRL)
THC MMIO Port
THC PCI Configuration
UART Additional MMIO
UART DMA
UART MMIO
UART PCI Configuration
USB MMIO
USB PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration

DAP USB 3.0 Port <N> Status (DAP_ESS_PORT_STATUS_REG_0_MMIO) – Offset 8acc

Control and status registers for all DRD eSS links.
All bits in this register must be in the Always ON Power domain (un-gated SUS or AON as appropriate).
The register applies to individual port. The offset of each port: 0x8ACC + N*0x10.
For example:
Port 0 offset: 0x8ACC
Port 1 offset: 0x8ADC
Port 2 offset: 0x8AEC
...

Bit Range	Default	Access	Field Name and Description
31:16	0h	RO	Reserved (RSVD1) Hardwired to 0.
15	0h	RO	Hardware VBus (HARDWARE_VBUS) Indicates live value of HW VBus signal. This bit only applies to Port 0 when configured as micro AB
14	0h	RO	Reserved
13:8	0h	RO	Reserved (RSVD2) Hardwired to 0.
7:0	10h	RO/V	Operation State (OPERATION_STATE) This field reflect live value of the DRD operation states with one-hot encodings stipulated as follows: 01h: Host 02h: Disconnected 04h: USB3 Reset (USB3RESET) 08h: Device 10h: PHY initialization 40h: DBC 80h: Over-subscribed device Others: Reserved Due to clock crossing uncertainties, more than 1 bit may be set, or none at all, while states are transitioning. USB2 PHY needs NOT be initialized. As such, the PHY initialization state carries no practical meaning herein.

GLOBAL TIME SYNC CAP REG (GLOBAL_TIME_SYNC_CAP_REG)

DAP USB 3.0 Port <N> Control 1 (DAP_ESS_PORT_CONTROL_1_REG_0_MMIO) GLOBAL TIME SYNC CAP REG (GLOBAL_TIME_SYNC_CAP_REG)

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Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

DAP USB 3.0 Port <N> Status (DAP_ESS_PORT_STATUS_REG_0_MMIO) – Offset 8acc