Device Capabilities 2 (DCAP2) – Offset 64 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

Device Capabilities 2 (DCAP2) – Offset 64

This is the Device Capabilities 2 registers. Refer description for each individual field below for more details of the register functionality.

Bit Range	Default	Access	Field Name and Description
31:24	0h	RO	Reserved (RSVD_M) Reserved
23:22	2h	RW/O	Max End-End TLP Prefixes (MEETLPP) Indicates the maximum number of End-End TLP Prefixes supported by this Function. TLPs received by this Function that contain more End-End TLP Prefixes than are supported must be handled as Malformed TLPs. Values are: 01b: 1 End-End TLP Prefix 10b: 2 End-End TLP Prefixes 11b: 3 End-End TLP Prefixes 00b: 4 End-End TLP Prefixes If End-End TLP Prefix Supported is Clear, this field is RsvdP.
21	1h	RW/O	End-End TLP Prefix Supported (EETLPPS) Indicates whether End-End TLP Prefix support is offered by a Function. Values are: 0b: No Support. 1b: Support is provided to receive TLPs containing End-End TLP Prefixes.
20	1h	RW/O	Extended Fmt Field Supported (EFFS) If Set, the Function supports the 3 bit definition of the Fmt field. If Clear, the Function supports a 2 bit definition of the Fmt field. Must be Set for Functions that support End-End TLP Prefixes. All Functions in an Upstream Port must have the same value for this bit. Each Downstream Port of a component may have a different value for this bit. It is strongly recommended that Functions support the 3 bit definition of the Fmt field.
19:18	2h	RW/O	Optimized Buffer Flush/Fill Supported (OBFFS) 00b: OBFF is not supported. 01b: OBFF is supported using Message signaling only. 10b: OBFF is supported using WAKE signaling only. 11b: OBFF is supported using WAKE and Message signaling. BIOS should program this field to 00b or 10b during system intialization to advertise the level of hardware OBFF support to software. BIOS should never program this field to 01b or 11b since OBFF messaging is not supported. Note: OBFF is not supported. BIOS should program this field to 00b.
17	0h	RW/O	10-Bit Tag Requester Supported (PX10BTRS) If this bit is Set, the Function supports 10-Bit Tag Requester capability - otherwise, the Function does not. This bit must not be Set if the 10-Bit Tag Completer Supported bit is Clear. Register Attribute: Static.
16	0h	RW/O	10-Bit Tag Completer Supported (PX10BTCS) If this bit is Set, the Function supports 10-Bit Tag Completer capability - otherwise, the Function does not. Register Attribute: Static.
15:12	0h	RO	Reserved
11	1h	RW/O	LTR Mechanism Supported (LTRMS) A value of 1b indicates support for the optional Latency Tolerance Reporting (LTR) mechanism capability. BIOS must write to this register with either a 1 or a 0 to enable/disable the root port from declaring support for the LTR capability.
10	0h	RO	Reserved
9	0h	RW/O	CAS Completer 128-bit Supported (AC128BS) Applicable to Functions with Memory Space BARs as well as all Root Ports - must be 0b otherwise. This bit must be set to 1b if the Function supports this optional capability.
8	0h	RW/O	AtomicOp Completer 64-bit Supported (AC64BS) Applicable to Functions with Memory Space BARs as well as all Root Ports - must be 0b otherwise. Includes FetchAdd, Swap, and CAS AtomicOps. This bit must be set to 1b if the Function supports this optional capability
7	0h	RW/O	AtomicOp Completer 32-bit Supported (AC32BS) Applicable to Functions with Memory Space BARs as well as all Root Ports - must be 0b otherwise. Includes FetchAdd, Swap, and CAS AtomicOps. This bit must be set to 1b if the Function supports this optional capability
6	0h	RW/O	Atomic Routing Supported (ARS) This bit must be set to 1b if the Port supports this optional capability
5	1h	RO	ARI Forwarding Supported (AFS) Applicable only to Switch Downstream Ports and Root Ports - must be 0b for other Function types. This bit must be set to 1b if a Switch Downstream Port or Root Port supports this optional capability. Register Attribute: Static.
4	1h	RO	Completion Timeout Disable Supported (CTDS) A value of 1b indicates support for the Completion Timeout Disable mechanism.
3:0	7h	RO	Completion Timeout Ranges Supported (CTRS) This field indicates device support for the optional Completion Timeout programmability mechanism. This mechanism allows system software to modify the Completion Timeout value. This field is applicable only to Root Ports, Endpoints that issue requests on their own behalf, and PCI Express to PCI/PCI-X Bridges that take ownership of requests issued on PCI Express. For all other devices this field is reserved and must be hardwired to 0000b. Four time value ranges are defined: Range A: 50us to 10ms Range B: 10ms to 250ms Range C: 250ms to 4s Range D: 4s to 64s Bits are set according to the table below to show timeout value ranges supported. 0000b Completion Timeout programming not supported. 0001b Range A 0010b Range B 0011b Ranges A & B 0110b Ranges B & C 0111b Ranges A, B & C <-- This is what Root Port supports 1110b Ranges B, C & D 1111b Ranges A, B, C & D All other values are reserved.