Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2
ID | Date | Version | Classification |
---|---|---|---|
834576 | 10/10/2024 | 001 | Public |
Device Capabilities (DCAP) – Offset 44
This is the Device Capabilities registers. Refer description for each individual field below for more details of the register functionality.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:29 | 0h | RO | Reserved (RSVD_M) Reserved. |
28 | 0h | RO | Function Level Reset Capable (FLRC) Not supported in Root Ports |
27:26 | 0h | RO | Captured Slot Power Limit Scale (CSPS) Not supported. |
25:18 | 0h | RO | Captured Slot Power Limit Value (CSPV) Not supported. |
17:16 | 0h | RO | Reserved |
15 | 1h | RO | Role Based Error Reporting (RBER) Indicates that this device implements the functionality defined in the Error Reporting ECN as required by the PCI Express 1.1 spec. |
14 | 0h | RO | Reserved. On previous version of the specification this was Power Indicator Present (PIP) Reserved |
13 | 0h | RO | Reserved. On previous version of the specification this was Attention Indicator Present (AIP) Reserved |
12 | 0h | RO | Reserved. On previous version of the specification this was Attention Button Present (ABP) Reserved |
11:9 | 0h | RO | Endpoint L1 Acceptable Latency (E1AL) Reserved for root ports. |
8:6 | 0h | RO | Endpoint L0s Acceptable Latency (E0AL) Reserved for Root port. |
5 | 0h | RW/O | Extended Tag Field Supported (ETFS) The Root Port never needs to initiate a transaction as a Requester with the Extended Tag bits being set. This bit does not affect the root ports ability to forward requests as a bridge as the root port always supports forwarding requests with extended tags. |
4:3 | 0h | RO | Phantom Functions Supported (PFS) No phantom functions supported |
2:0 | 1h | RW/L | Max Payload Size Supported (MPS) Max Payload Size of up to 256B is supported. Programming this field to any values other than 128B or 256B max payload size will result in aliasing to 128B max payload size. |