Device Command and Status (PCI_COM_STAT) – Offset 4 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

Device Command and Status (PCI_COM_STAT) – Offset 4

Bit Range	Default	Access	Field Name and Description
31	0x0	RW/1C	Detected Parity Error (DET_PAR_ERR) Detected Parity Error
30	0x0	RW/1C	Signaled System Error (SIG_SYS_ERR) Signaled System Error
29	0x0	RW/1C	Received Master Abort (REC_MAS_ABRT) Received Master Abort
28	0x0	RW/1C	Received Target Abort (REC_TAR_ABRT) Received Target Abort
27	0x0	RW/1C	Signaled Target Abort (SIG_TAR_ABRT) Signaled Target Abort.
26:25	0x0	RO	DEVSEL Timing (DEVSEL_TIMING) Does not apply. Hardwired to 0
24	0x0	RW/1C	Master Data Parity Error (MAS_DATA_PAR_ER) Master Data Parity Error
23	0x0	RO	Fast Back to Back Transaction Capable (FAST_BTB_TCAP) Does not apply. Hardwired to 0.
22	0h	RO	Reserved
21	0x0	RO	66 MHz Capable (OLF_FREQ_CAP) Does not apply. Hardwired to 0
20	0x1	RO	Capability List (CAP_LST) Hardwired to 1
19	0x0	RO	Interrupt Status (INTRPT_STS) Reflects the state of the interrupt in the device
18:11	0h	RO	Reserved
10	0x0	RW	Interrupt Disable (INTRPT_DIS) Controls the ability of the device to generate legacy interrupt messages. 0 = Enable. 1 = Disable.
9	0x0	RO	Fast Back to Back Enable (FAST_BTB_TNSCEN) Does not apply. Hardwired to 0
8	0x0	RW	SERR Enable (SERR_EN) Enable SERR# to be generated if this bit is set
7	0x0	RO	Wait Cycle Control (IDSEL_STEP_W_CY) Does not apply. Hardwired to 0
6	0x0	RW	Parity Error Enable (PAR_ERR) This bit is set to 1 to enable response to parity errors when detected.
5	0x0	RO	VGA Palette Snoop (VGA_PALT_SNOOP) Does not apply. Hardwired to 0.
4	0x0	RO	Memory Write and Invalidate (MEM_WR_INVALD) Does not apply. Hardwired to 0.
3	0x0	RO	Special Cycle Enable (SPEC_CYC_ENB) Does not apply. Hardwired to 0.
2	0x0	RW	Bus Master Enable (BUS_MAS) Bus Master Enable
1	0x0	RW	Memory Space Access Enable (MEM_SP_ACC) Memory Space access enable
0	0x0	RO	IO Space Access Enable (IO_SPC_AC_EN_0) IO Space access enable