Device Control (DCTL) – Offset c704 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

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Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

Device Control (DCTL) – Offset c704

Bit Range	Default	Access	Field Name and Description
31	0h	RW	Run/Stop (RUN_STOP) The software writes 1 to this bit to start the device controller operation.To stop the device controller operation, the software must remove any active transfers and write 0 to this bit. When the controller is stopped, it sets the DSTS.DevCtrlHlt bit when the core is idle and the lower layer finishes the disconnect process. The Run/Stop bit must be used in following cases as specified: 1.After power-on reset and CSR initialization, the software must write 1 to this bit to start the device controller. The controller does not signal connect to the host until this bit is set. 2.The software uses this bit to control the device controller to perform a soft disconnect. When the software writes 0 to this bit, the host does not see that the device is connected. The device controller stays in the disconnected state until the software writes 1 to this bit. The minimum duration of keeping this bit cleared: SS: 30ms HS/FS/LS: 10ms If the software attempts a connect after the soft disconnect or detects adisconnect event, it must set DCTL[8:5] to 5 before reasserting the Run/Stopbit. 3.When the USB or Link is in a lower power state and the Two Power Rails configuration is selected, software writes 0 to this bit to indicate that it is going to turn off the Core Power Rail. After the software turns on the Core Power Rail again and re-initializes the device controller, it must set this bit to start the device controller.
30	0h	RW	Core Soft Reset (CSFTRST) Resets the all clock domains
29	0h	RO	reserved_29 (reserved_29)
28:24	0h	RW	HIRD Threshold (HIRDTHRES) The core asserts output signals utmi_l1_suspend_n and utmi_sleep_n on the basis of this signal: The core asserts utmi_l1_suspend_n to put the PHY into Deep Low-Power mode in L1 when both of the following are true: -HIRD value is greater than or equal to the value in DCTL.HIRD_Thres[3:0] -HIRD_Thres[4] is set to 1'b1. The core asserts utmi_sleep_n on L1 when one of the following is true: -If the HIRD value is less than HIRD_Thres[3:0] or -HIRD_Thres[4] is set to 1'b0. Note: This field must be set to ‘0’ during SuperSpeed mode of operation.
23:20	fh	RW	LPM NYET Response Threshold (LPM_NYET_thres) Handshake response to LPM token specified by device application
19	0h	RW	Keep Connect (KeepConnect) When '1', this bit enables the save and restore programming model by preventing the core from disconnecting from the host when DCTL.RunStop is set to '0'. It also enables the Hibernation Request Event to be generated when the link goes to U3 or L2. The device core disconnects from the host when DCTL.RunStop is set to '0'. This bit indicates whether to preserve this behavior ('0'), or if the core should not disconnect when RunStop is set to 0 ('1').This bit also prevents the LTSSM from automatically going to U0/L0 when the host requests resume from U3/L2.
18	0h	RW	L1 Hibernation Enable (L1HibernationEn) When this bit is set along with KeepConnect, the device core generates a Hibernation Request Event if L1 is enabled and the HIRD value in the LPM token is larger than the threshold programmed in DCTL.HIRD_Thres. The core will not exit the LPM L1 state until software writes Recovery into the DCTL.ULStChngReq field. This prevents corner cases where the device is entering hibernation at the same time the host is attempting to exit L1.
17	0h	RW	Controller Restore State (CRS) This command initiates the restore process. When software sets this bit to '1', the controller immediately sets DSTS.RSS to '1'. When the controller has finished the restore process, it sets DSTS.RSS to '0'. Note: When read, this field always returns '0'.
16	0h	RW	Controller Save State (CSS) This command initiates the save process. When software sets this bit to '1', the controller immediately sets DSTS.SSS to '1'. When the controller has finished the save process, it sets DSTS.SSS to '0'. Note: When read, this field always returns '0'.
15:13	0h	RO	Reserved
12	0h	RW	Initiate U1 Enable (INITU2ENA) 1'b0: May not initiate U2 (default) 1'b1: May initiate U2 On USB reset, hardware clears this bit to ”0”. Software sets this bit after receiving SetFeature(U2_ENABLE), and clears this bit when ClearFeature(U2_ENABLE) is received.If DCTL[11] (AcceptU2Ena) is 0, the link immediately exits U2 state.
11	0h	RW	Accept U1 Enable (ACCEPTU2ENA) 1'b0: Reject U2 except when Force_LinkPM_Accept bit is set (default) 1'b1: Core accepts transition to U2 state if nothing is pending on the application side. On USB reset, hardware clears this bit to ”0”. Software sets this bit after receiving a SetConfiguration command
10	0h	RW	Initiate U1 Enable (INITU1ENA) 1'b0: May not initiate U1 1'b1: May initiate U1 On USB reset, hardware clears this bit to “0”. Software sets this bit after receiving SetFeature(U1_ENABLE), and clears this bit when ClearFeature(U1_ENABLE) is received. If DCTL[9] (AcceptU1Ena) is 0, the link immediately exits U1 state.
9	0h	RW	ACCEPTU1ENA (ACCEPTU1ENA) 1'b0: Core rejects U1 except when Force_LinkPM_Accept bit is set (default) 1'b1: Core accepts transition to U1 state if nothing is pending on the application side. On USB reset, hardware clears this bit to “0”. Software sets this bit after receiving a SetConfiguration command.
8:5	0h	WO	USB/Link State Change Request (ULSTCHNGREQ) Software writes this field to issue a USB/Link state change request. A change in this field indicates a new request to the core. If software wants to issue the same request back-to-back, it must write a 0 to this field between the two requests. The result of the state change request is reflected in the USB/Link State in DSTS. These bits are self-cleared on the MAC Layer exiting suspended state. If software is updating other fields of the DCTL register and not intending to force any link state change, then it must write a 0 to this field. SS Compliance mode is normally entered and controlled by the remote link partner. Alternatively, the local link can be forced directly into Compliance mode by resetting the SS link with the RUN/STOP bit set to zero. If then '10' is written to the USB/Link State Change field and '1' to RUN/STOP, the Link will go to Compliance. Once in Compliance, 'zero' and '10' may alternately be written to this field to advance the compliance pattern. In SS mode: ValueRequested Link State Transition: 0: No Action 4: SS.Disabled 5: Rx.Detect 6: SS.Inactive 8:Recovery 10:Compliance Others:Reserved In HS/FS/LS mode: ValueRequested USB state transition 8: Remote wakeup request Others:Reserved The Remote wakeup request should be issued 2µs after the device goes into suspend state. Note: After coming out of hibernation, software should write 8 (Recovery) into this field to confirm exit from the suspended state
4:0	0h	RO	Reserved