Device Control (DEVC) – Offset 88 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

Device Control (DEVC) – Offset 88

This register controls PCI Express device specific parameters.

Bit Range	Default	Access	Field Name and Description
15	0h	WO	Initiate FLR (IF) Used to initiate FLR transition. A write of 1 initiates FLR transition. Since hardware must not respond to any cycles until FLR completion, the read value by software from this bit is 0.
14:12	2h	RW	Max Read Request Size (MRRS) This field sets the maximum Read Request size for the Function as a Requester. The Function must not generate Read Requests with size exceeding the set value. Defined encodings for this field are: 000: 128 B 001: 256 B 010: 512 B 011: 1024 B 100: 2048 B 101: 4096 B 110 - 111: Reserved
11	1h	RW	Enable No Snoop (NSNPEN) When set to 1 (or EM2.FNSNPEN = 1) the ACE IP is permitted to set the No Snoop bit in the Requester Attributes of a bus master transaction. In this case VC0 or VC1 may be used for isochronous transfers. When set to 0 (and EM2.FNSNPEN = 0) the ACE IP will not set the No Snoop bit. In the case isochronous transfers will not use VC1(VCi) even if it is enabled since VC1 is never snooped. Isochronous transfers will use VC0.
10	0h	RO	Auxiliary (AUX) Hardwired to 0 indicating the ACE IP does not draw AUX power (outside of PME usage).
9	0h	RO	Phantom Functions Enable (PFEN) Hardwired to 0 disabling phantom functions.
8	0h	RO	Extended Tag Field Enable (ETEN) Hardwired to 0 enabling 5-bit tag.
7:5	0h	RO	Max Payload Size (MAXPAY) Hardwired to 000 indicating 128 B.
4	0h	RO	Enable Relaxed Ordering (ROEN) Hardwired to 0 disabling relaxed ordering.
3	0h	RW	Unsupported Request Reporting Enable (URREN) This bit, in conjunction with other bits, controls the signaling of Unsupported Request Errors by sending error Messages.
2	0h	RW	Fatal Error Reporting Enable (FEREN) This bit, in conjunction with other bits, controls sending ERR_FATAL Messages.
1	0h	RW	Non-Fatal Error Reporting Enable (NFEREN) This bit, in conjunction with other bits, controls sending ERR_NONFATAL Messages.
0	0h	RW	Correctable Error Reporting Enable (CEREN) This bit, in conjunction with other bits, controls sending ERR_COR Messages.