Device Idle Control (DEVIDLE_CONTROL) – Offset 24c - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Introduction
CNVi WiFi* PCI Configuration
eSPI PCI Configuration
eSPI PCR
GPIO Commumity 0
GPIO Commumity 1
GPIO Commumity 2
GPIO Commumity 3
GPIO Commumity 4
GPIO Commumity 5
GSPI Additional MMIO
GSPI DMA
GSPI MMIO
GSPI PCI Configuration
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I2C MMIO
I3C / I2C / UART / GSPI PCR
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IDE-Redirect (IDE-R) PCI Configuration
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Integrated Sensor Hub (ISH) PCI Configuration
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Intel(R) Management Engine Interface (MEI) PCI Configuration
Intel® High Definition Audio MMIO
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Intergrated GbE MMIO
Keyboard and Text (KT) PCI Configuration
P2SB PCI Configuration
PCIe* PCI Configuration
PMC I/O Based
PMC MMIO
PMC PCI Configuration
PMC SSRAM PCI Configuration
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RTC PCR
SATA ABAR
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- AHCI Index Register (INDEX)
- AHCI Data Register (DATA)
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- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
- MSI-X Pending Bit Array QW 1 (MXPQW0_DW1)
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SATA Port 0 ABAR
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SATA Port 2 ABAR
SATA Port 3 ABAR
SATA Port 4 ABAR
SATA Port 5 ABAR
SATA Port 6 ABAR
SATA Port 7 ABAR
SMBus MMIO and I/O
SMBus PCI Configuration
SMBus PCR
SMBus TCO I/O
SPI MMIO
SPI PCI Configuration
THC MMIO Common
- Device Idle Control Register (THC_M_CMN_DEVIDLECTRL)
- THC LTR Control Register (THC_M_CMN_LTR_CTRL)
THC MMIO Port
THC PCI Configuration
UART Additional MMIO
UART DMA
UART MMIO
UART PCI Configuration
USB MMIO
USB PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration

Device Idle Control (DEVIDLE_CONTROL) – Offset 24c

Bit Range	Default	Access	Field Name and Description
31:5	0h	NA	reserved (reserved0) reserved
4	0h	RO	Inturrupt Request Capable (intr_req_capable) Set to 1 by HW if it is capable of generating an interrupt on command completion, else 0.
3	1h	RW/1C	Restore Required (restore_required) When set (by HW), SW must restore state to the IP. The state may have been lost due to a reset or full power lost. SW clears the bit by writing a 1. This bit will be set on initial power up.
2	0h	RW	Device Idle (devidle) SW sets this bit to 1 to move the function into the DevIdle state. Writing this bit to 0 will return the function to the fully active D0 state (D0i0)
1	0h	NA	Interrupt Request (intr_req) Reserved
0	0h	RO	Command In Progress (cmd_in_progress) HW sets this bit on a 1->0 or 0->1 transition of DEVIDLE. While set, the other bits in this register are not valid and it is illegal for SW to write to any bit in this register. HW clears this bit upon completing the DevIdle transition command. When clear, all the other bits in the register are valid and SW may write to any bit. If Interrupt Request (IR) was set for the current command, HW may clear this bit before the interrupt has been made visible to SW, since when SW actually handles a particular interrupt is not visible to the HW. SW writes to this bit have no effect.

Capabilities (CAPABLITIES)

Address High (REMAP_ADDR_HI) Capabilities (CAPABLITIES)