Device Idle Power On Latency (HECI1_DEVIDLEPOL) – Offset b4 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

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Device Idle Power On Latency (HECI1_DEVIDLEPOL) – Offset b4

Device Idle Power On Latency

Bit Range	Default	Access	Field Name and Description
15:13	0h	RO	Reserved (RSVD_15_13) Reserved.
12:10	3h	RW/O	Power On Latency Scale (POLS) Latency Scale multiplier: 010: 1us 011: 32us All other settings are reserved (not enforced by HW). The value of this register is multiplied with the Power On Latency Value (POLV) to provide the DevIdle power on exit latency multiplier scale from 1us to 32ms. This register is defined to be RWO (read-write-once) to allow BIOS to set the initial value. This register is undefined if the device idle valid bit is 1'b0.
9:0	138h	RW/O	Power On Latency Value (POLV) 10-bit value that is multiplied by the Power On Latency Scale. A value of 0 indicates a power on latency of less than 1us. This register is defined to be RWO (read-write-once) to allow BIOS to set the initial value. This register is undefined if the device idle valid bit is 1'b0.

Bit Range

Default

Access

Field Name and Description

15:13

Reserved (RSVD_15_13)

Reserved.

12:10

RW/O

Power On Latency Scale (POLS)

Latency Scale multiplier:

010: 1us

011: 32us

All other settings are reserved (not enforced by HW).

The value of this register is multiplied with the Power On Latency Value (POLV) to provide the
DevIdle power on exit latency multiplier scale from 1us to 32ms.

This register is defined to be RWO (read-write-once) to allow BIOS to set the initial value.

This register is undefined if the device idle valid bit is 1'b0.

9:0

138h

RW/O

Power On Latency Value (POLV)

10-bit value that is multiplied by the Power On Latency Scale.

A value of 0 indicates a power on latency of less than 1us.

This register is defined to be RWO (read-write-once) to allow BIOS to set the initial value.

This register is undefined if the device idle valid bit is 1'b0.

DevIdle Power Control Enabled Register (HECI1_PWRCTRLEN)

Device Idle Pointer Register (HECI1_DEVIDLEPTR) DevIdle Power Control Enabled Register (HECI1_PWRCTRLEN)