Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2
ID | Date | Version | Classification |
---|---|---|---|
834576 | 10/10/2024 | 001 | Public |
Device Physical Endpoint-n Command (DEPCMD_0) – Offset c80c
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:16 | 0h | RW | Command Parameters (COMMANDPARAM) When this register is written: |
15:12 | 0h | RW | Command Completion Status (CMDSTATUS) Additional information about the completion of this command is available in this field. |
11 | 0h | RW | HighPriority/ ForceRM (HIPRI_FORCERM) HighPriority: Only valid for Start |
10 | 0h | RW | Command Active (CMDACT) Software sets this bit to 1 to enable the device |
9 | 0h | RO | Reserved |
8 | 0h | RW | Command Interrupt on Complete (CMDIOC) When this bit is set, the device controller issues a generic Endpoint Command Complete event after executing the command. Note that this interrupt is mapped to DEPCFG.IntrNum. When the DEPCFG command is executed, the command interrupt on completion goes to the interrupt pointed by the DEPCFG.IntrNum in the current command. |
7:4 | 0h | RO | Reserved |
3:0 | 0h | RW | Command Type (CMDTYP) Specifies the type of command the software driver is |