Device Status (DS) – Offset 6 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Introduction
CNVi WiFi* PCI Configuration
eSPI PCI Configuration
eSPI PCR
GPIO Commumity 0
GPIO Commumity 1
GPIO Commumity 2
GPIO Commumity 3
GPIO Commumity 4
GPIO Commumity 5
GSPI Additional MMIO
GSPI DMA
GSPI MMIO
GSPI PCI Configuration
I2C Additional MMIO
I2C DMA
I2C MMIO
I3C / I2C / UART / GSPI PCR
I3C Additional MMIO
I3C DMA
I3C MMIO
I3C PCI Configuration
IDE-Redirect (IDE-R) PCI Configuration
Integrated GbE PCI Configuration
Integrated Sensor Hub (ISH) MMIO
Integrated Sensor Hub (ISH) PCI Configuration
Intel(R) Management Engine Interface (MEI) MMIO
Intel(R) Management Engine Interface (MEI) PCI Configuration
Intel® High Definition Audio MMIO
Intel® High Definition Audio PCI Configuration
Intergrated GbE MMIO
Keyboard and Text (KT) PCI Configuration
P2SB PCI Configuration
PCIe* PCI Configuration
PMC I/O Based
PMC MMIO
PMC PCI Configuration
PMC SSRAM PCI Configuration
RTC Index
RTC PCR
SATA ABAR
SATA AIDPBA
- AHCI Index Register (INDEX)
- AHCI Data Register (DATA)
SATA Initialization (SIR) Index
SATA MXPBA
- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
- MSI-X Pending Bit Array QW 1 (MXPQW0_DW1)
SATA MXTBA
SATA PCI Configuration
SATA Port 0 ABAR
SATA Port 1 ABAR
SATA Port 2 ABAR
SATA Port 3 ABAR
SATA Port 4 ABAR
SATA Port 5 ABAR
SATA Port 6 ABAR
SATA Port 7 ABAR
SMBus MMIO and I/O
SMBus PCI Configuration
SMBus PCR
SMBus TCO I/O
SPI MMIO
SPI PCI Configuration
THC MMIO Common
- Device Idle Control Register (THC_M_CMN_DEVIDLECTRL)
- THC LTR Control Register (THC_M_CMN_LTR_CTRL)
THC MMIO Port
THC PCI Configuration
UART Additional MMIO
UART DMA
UART MMIO
UART PCI Configuration
USB MMIO
USB PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration

Device Status (DS) – Offset 6

Device Status

Bit Range	Default	Access	Field Name and Description
15	0h	RW/1C	Detected Parity Error (DPE) Detected Parity Error
14	0h	RW/1C	Signaled System Error (SSE) Signaled System Error
13	0h	RO	Received Master Abort (RMA) Reserved as 0.
12	0h	RO	Received Target Abort (RTA) Reserved as '0'.
11	0h	RW/1C	Signaled Target-Abort Status (STA) Reserved as 0.
10:9	1h	RO	DEVSEL# Timing Status (DEVT) This 2-bit field defines the timing for DEVSEL# assertion. These read only bits indicate the Intel PCH's DEVSEL# timing when performing a positive decode. Note: Intel PCH generates DEVSEL# with medium time. Note: It is not clear if a PCI master can write to SMBus controller.
8	0h	RO	Data Parity Error Detected (DPED) Reserved as 0.
7	1h	RO	Fast Back-to-Back Capable (FBC) Reserved as '1'.
6	0h	RO	User Definable Features (UDF) Reserved as 0.
5	0h	RO	66 MHz Capable (C_66M) Reserved as 0.
4	0h	RO	Capabilities List Indicator (CLI) Hardwired to 0 because there are no capability list structures in this function.
3	0h	RO	Interrupt Status (INTS) This bit indicates that an interrupt is pending. It is independent from the state of the Interrupt Enable bit in the command register.
2:0	0h	RO	Reserved (RSVD) Reserved

Revision ID (RID)

Command Register (CMD) Revision ID (RID)

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Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Device Status (DS) – Offset 6