Device Status (STS_MMIO) – Offset 8606 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

Device Status (STS_MMIO) – Offset 8606

Device Status

Bit Range	Default	Access	Field Name and Description
15	0h	RW/1C	Detected Parity Error (DPE) This bit is set by the Intel PCH whenever a parity error is seen on the internal interface to the XHC host controller, regardless of the setting of bit 6 or bit 8 in the Command register or any other conditions. Software clears this bit by writing a 1 to this bit location.
14	0h	RW/1C	Signaled System Error (SSE) This bit is set by the Intel PCH whenever it signals SERR# (internally). The SERR_EN bit (bit 8 in the Command Register) must be 1 for this bit to be set. See error handling section for complete list of conditions handled. Software clears this bit by writing a 1 to this bit location.
13	0h	RW/1C	Received Master-Abort Status (RMA) This bit is set when XHC, as a master, receives a master-abort status on a memory access. This is treated as a Host Error and halts the DMA engines. Software clears this bit by writing a 1 to this bit location.
12	0h	RW/1C	Received Target Abort Status (RTA) This bit is set when XHC, as a master, receives a target abort status on a memory access. This is treated as a Host Error and halts the DMA engines. Software clears this bit by writing a 1 to this bit location.
11	0h	RW/1C	Signaled Target-Abort Status (STA) This bit is used to indicate when the XHC function responds to a cycle with a target abort.
10:9	1h	RO	DEVSEL Timing Status (DEVT) This 2-bit field defines the timing for DEVSEL# assertion. Read-Only.
8	0h	RW/1C	Master Data Parity Error Detected (MDPED) This bit is set by the Intel PCH whenever a data parity error is detected on a XHC read completion packet on the internal interface to the XHC host controller and bit 6 of the Command register is set to 1. Software clears this bit by writing a 1 to this bit location.
7	1h	RO	Fast Back-to-Back Capable (FBBC) Reserved as 1 Read-Only.
6	0h	RO	User Definable Features (UDF) Reserved as 0. Read-Only.
5	0h	RO	66 MHz Capable (MC) Reserved as 0. Read-Only.
4	1h	RO	Capabilities List (CL) Hardwired to 1 indicating that offset 34h contains a valid capabilities pointer.
3	0h	RO/V	Interrupt Status (INTR_STS) This read-only bit reflects the state of this function's interrupt at the input of the enable/disable logic. This bit is a 1 when the interrupt is asserted. This bit will be 0 when the interrupt is deasserted. The value reported in this bit is independent of the value in the Interrupt Enable bit.
2:0	0h	RO	Reserved (RSVD) Reserved