DMA Channel Enable (ChEnReg) – Offset ba0 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

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DMA Channel Enable (ChEnReg) – Offset ba0

This is the DMA Channel Enable Register. If software needs to set up a new channel, then it can read this register in order to find out which channels are currently inactive, it can then enable an inactive channel with the required priority.
All bits of this register are cleared to 0 when the global DMA channel enable bit, DmaCfgReg(0), is 0. When the global channel enable bit is 0, then a write to the ChEnReg register is ignored and a read will always read back 0. The channel
enable bit, ChEnReg.CH_EN, is written only if the corresponding channel write enable bit, ChEnReg.CH_EN_WE, is asserted on the same OCP write transfer.

Bit Range	Default	Access	Field Name and Description
31:10	0h	NA	RSVD1_2 (RSVD1_2) Reserved
9:8	0h	WO	CH_EN_WE (CH_EN_WE) Channel enable write enable.
7:2	0h	NA	RSVD0 (RSVD0) Reserved
1:0	0h	RW	CH_EN (CH_EN) Enables/Disables the channel. Setting this bit enables a channel, clearing this bit disables the channel. 0 = Disable the Channel 1 = Enable the Channel The ChEnReg.CH_EN bit is automatically cleared by hardware to disable the channel after the last OCP transfer of the DMA transfer to the destination has completed. Software can therefore poll this bit to determine when this channel is free for a new DMA transfer.

Global DMA Configuration (GLOBAL_CFG)

DMA Configuration (DmaCfgReg) Global DMA Configuration (GLOBAL_CFG)