DMA Transfer Configuration High 0 (CFG_HI0) – Offset 844 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

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DMA Transfer Configuration High 0 (CFG_HI0) – Offset 844

This register contains fields that configure the DMA transfer. The channel configuration registerremains fixed for all blocks of a multi-block transfer. This Register should be programmed to enabling the channel

Bit Range	Default	Access	Field Name and Description
31:28	0h	NA	Reserved_31_28 (Reserved_31_28) Reserved
27:18	0h	RW	WR_ISSUE_THD (WR_ISSUE_THD) Write Issue Threshold. Value ranges from 0 to (2^10-1 = 1023) but should not exceed maximum Write burst size = (2 ^ DST_MSIZE)*TW.
17:8	0h	RW	RD_ISSUE_THD (RD_ISSUE_THD) Read Issue Threshold. Value ranges from 0 to (2^10-1 = 1023) but should not exceed maximum Read burst size = (2 ^ SRC_MSIZE)*TW.
7:4	0h	RW	DST_PER (DST_PER) Destination Peripheral ID : Assigns a hardware handshaking interface (0 - 15) to the destination of channel n. The channel can then communicate with the destination peripheral connected to that interface through the assigned hardware handshaking interface.
3:0	0h	RW	SRC_PER (SRC_PER) Source Peripheral ID : Assigns a hardware handshaking interface (0 - 15) to the source of channel n. The channel can then communicate with the source peripheral connected to that interface through the assigned hardware handshaking interface.

Source Gather 0 (SGR0)

DMA Transfer Configuration Low 0 (CFG_LO0) Source Gather 0 (SGR0)