DMA Transfer Configuration Low 1 (CFG_LO1) – Offset 898 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

DMA Transfer Configuration Low 1 (CFG_LO1) – Offset 898

Same description as CFG_LO0

Bit Range	Default	Access	Field Name and Description
31	0h	RW	RELOAD_DST (RELOAD_DST) Automatic Destination Reload. The DARn register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated
30	0h	RW	RELOAD_SRC (RELOAD_SRC) Automatic Source Reload. The SARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated.
29:22	0h	NA	Reserved_29_22 (Reserved_29_22) Reserved
21	0h	RW	SRC_OPT_BL (SRC_OPT_BL) Optimize Source Burst Length : 0 = Writes will use only BL=1 or BL=(2 ^ SRC_MSIZE) 1 = Writes will use (1 (= BL (= (2 ^ SRC_MSIZE))
20	0h	RW	DST_OPT_BL (DST_OPT_BL) Optimize Destination Burst Length : 0 = Writes will use only BL=1 or BL=(2 ^ DST_MSIZE) 1 = Writes will use (1 (= BL (= (2 ^ DST_MSIZE))
19	0h	RW	SRC_HS_POL (SRC_HS_POL) Source Handshaking Interface Polarity. 0 = Active high 1 = Active low
18	0h	RW	DST_HS_POL (DST_HS_POL) Destination Handshaking Interface Polarity. 0 = Active high 1 = Active low
17:11	0h	NA	Reserved_17_11 (Reserved_17_11) Reserved
10	0h	RW	CH_DRAIN (CH_DRAIN) Forces channel FIFO to drain while in suspension. This bit has effect only when CH_SUSPEND ia asserted
9	1h	RO	FIFO_EMPTY (FIFO_EMPTY) Indicates if there is data left in the channel FIFO. Can be used in conjunction with CFGx.CH_SUSP to cleanly disable a channel. 1 = Channel FIFO empty 0 = Channel FIFO not empty
8	0h	RW	CH_SUSP (CH_SUSP) Channel Suspend. Suspends all DMA data transfers from the source until this bit is cleared. There is no guarantee that the current transaction will complete. Can also be used in conjunction with CFGx.FIFO_EMPTY to cleanly disable a channel without losing any data. 0 = Not suspended. 1 = Suspend DMA transfer from the source.
7	0h	RW	SS_UPD_EN (SS_UPD_EN) Source Status Update Enable. Source status information is fetched only from the location pointed to by the SSTATARn register, stored in the SSTATn register and written out to the SSTATn location of the LLI if SS_UPD_EN is high. This bit is ignored if (LLP_EN == 0) or (LLP_WB_EN == 0
6	0h	RW	DS_UPD_EN (DS_UPD_EN) Destination Status Update Enable. Destination status information is fetched only from the location pointed to by the DSTATARn register, stored in the DSTATn register and written out to the DSTATn location of the LLI if DS_UPD_EN is high. This bit is ignored if (LLP_EN == 0) or (LLP_WB_EN == 0)
5	0h	RW	CTL_HI_UPD_EN (CTL_HI_UPD_EN) CTL_HI Update Enable. If set, the CTL_HI register is written out to the CTL_HIn location of the LLI. This bit is ignored if (LLP_EN == 0) or (LLP_WB_EN == 0)
4	0h	RO	RSVD_4_4 (RSVD_4_4) Reserved
3	0h	RW	HSHAKE_NP_WR (HSHAKE_NP_WR) 0x1 : Issues Non-Posted writes on HW-Handshake on DMA Write Port 0x0 : Issues Posted writes on HW-Handshake on DMA Write Port (Except end-ofblock writes which will be Non-Posted)
2	0h	RW	ALL_NP_WR (ALL_NP_WR) 0x1 : Forces ALL writes to be Non-Posted on DMA Write Port 0x0 : Non-Posted Writes will only be used at end of block transfers and in HWHandshake (if HW_NP_WR=1); for all other cases, Posted Writes will be used
1	1h	RW	SRC_BURST_ALIGN (SRC_BURST_ALIGN) 0x1 : SRC Burst Transfers are broken at a Burst Length aligned boundary 0x0 : SRC Burst Transfers are not broken at a Burst Length aligned boundary
0	1h	RW	DST_BURST_ALIGN (DST_BURST_ALIGN) 0x1 : DST Burst Transfers are broken at a Burst Length aligned boundary 0x0 : DST Burst Transfers are not broken at a Burst Length aligned boundary