DMA Transfer Destination Address High 1 (DAR_HI1) – Offset 864 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Introduction
CNVi WiFi* PCI Configuration
eSPI PCI Configuration
eSPI PCR
GPIO Commumity 0
GPIO Commumity 1
GPIO Commumity 2
GPIO Commumity 3
GPIO Commumity 4
GPIO Commumity 5
GSPI Additional MMIO
GSPI DMA
GSPI MMIO
GSPI PCI Configuration
I2C Additional MMIO
I2C DMA
I2C MMIO
I3C / I2C / UART / GSPI PCR
I3C Additional MMIO
I3C DMA
I3C MMIO
I3C PCI Configuration
IDE-Redirect (IDE-R) PCI Configuration
Integrated GbE PCI Configuration
Integrated Sensor Hub (ISH) MMIO
Integrated Sensor Hub (ISH) PCI Configuration
Intel(R) Management Engine Interface (MEI) MMIO
Intel(R) Management Engine Interface (MEI) PCI Configuration
Intel® High Definition Audio MMIO
Intel® High Definition Audio PCI Configuration
Intergrated GbE MMIO
Keyboard and Text (KT) PCI Configuration
P2SB PCI Configuration
PCIe* PCI Configuration
PMC I/O Based
PMC MMIO
PMC PCI Configuration
PMC SSRAM PCI Configuration
RTC Index
RTC PCR
SATA ABAR
SATA AIDPBA
- AHCI Index Register (INDEX)
- AHCI Data Register (DATA)
SATA Initialization (SIR) Index
SATA MXPBA
- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
- MSI-X Pending Bit Array QW 1 (MXPQW0_DW1)
SATA MXTBA
SATA PCI Configuration
SATA Port 0 ABAR
SATA Port 1 ABAR
SATA Port 2 ABAR
SATA Port 3 ABAR
SATA Port 4 ABAR
SATA Port 5 ABAR
SATA Port 6 ABAR
SATA Port 7 ABAR
SMBus MMIO and I/O
SMBus PCI Configuration
SMBus PCR
SMBus TCO I/O
SPI MMIO
SPI PCI Configuration
THC MMIO Common
- Device Idle Control Register (THC_M_CMN_DEVIDLECTRL)
- THC LTR Control Register (THC_M_CMN_LTR_CTRL)
THC MMIO Port
THC PCI Configuration
UART Additional MMIO
UART DMA
UART MMIO
UART PCI Configuration
USB MMIO
USB PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration

DMA Transfer Destination Address High 1 (DAR_HI1) – Offset 864

Same description as DAR_HI0

Bit Range	Default	Access	Field Name and Description
31:0	0h	RW	DAR_HI (DAR_HI) Current Destination Address of DMA transfer. Updated after each destination transfer. The DINC field in the CTL_LO[n]: Control Register determines whether the address increments or is left unchanged on every destination transfer throughout the block transfer. When the channel is enabled (i.e. CH_EN is 1), the read back value will reflect the updated destination transfer addresses. However, when the channel is disabled, the original programmed value will be reflected when reading this register. It's important to notice the following: 1. Once the block transfer is in progress (i.e. when channel is enabled), the read-back value correlates with the OCP Write Address that one would see in an OCP tracker. 2. If the read to this register comes during a block transfer, the LAST DMA Write address sent on the OCP before the register read is what's reflected in the read-back value. 3. If the last DMA write was a burst write (i.e. burst length ) 1), the read-back value reflects the first address of the burst write since this is what gets sent on the OCP fabric. 4. If the read to the register occurred after the whole block got transferred, then the channel gets disabled and the returned value would be the original programmed value. 5. Since the read-back value is OCP based, only DW aligned addresses will be reflected (i.e. OCP Byte-Enable values would not be reflected) 6. Based on the above remarks, this value should be used as pseudo DMA write progress indicator when the channel is enabled and not an absolute one. Decrementing addresses are not supported

Bit Range

Default

Access

Field Name and Description

31:0

DAR_HI (DAR_HI)

Current Destination Address of DMA transfer.
Updated after each destination transfer. The DINC field in the CTL_LO[n]: Control
Register determines whether the address increments or is left unchanged on every
destination transfer throughout the block transfer. When the channel is enabled (i.e.
CH_EN is 1), the read back value will reflect the updated destination transfer addresses.
However, when the channel is disabled, the original programmed value will be reflected
when reading this register.
It's important to notice the following:
1. Once the block transfer is in progress (i.e. when channel is enabled), the read-back
value correlates with the OCP Write Address that one would see in an OCP tracker.
2. If the read to this register comes during a block transfer, the LAST DMA Write
address sent on the OCP before the register read is what's reflected in the read-back
value.
3. If the last DMA write was a burst write (i.e. burst length ) 1), the read-back value
reflects the first address of the burst write since this is what gets sent on the OCP fabric.
4. If the read to the register occurred after the whole block got transferred, then the
channel gets disabled and the returned value would be the original programmed value.
5. Since the read-back value is OCP based, only DW aligned addresses will be reflected
(i.e. OCP Byte-Enable values would not be reflected)
6. Based on the above remarks, this value should be used as pseudo DMA write
progress indicator when the channel is enabled and not an absolute one.
Decrementing addresses are not supported

Linked List Pointer Low 1 (LLP_LO1)

DMA Transfer Destination Address Low 1 (DAR_LO1) Linked List Pointer Low 1 (LLP_LO1)