DMA Transfer Destination Address Low 0 (DAR_LO0) – Offset 808 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

DMA Transfer Destination Address Low 0 (DAR_LO0) – Offset 808

The starting destination address is programmed by software before the DMA channel is enabled, or by an LLI update
before the start of the DMA transfer. While the DMA transfer is in progress, this register is updated to reflect the
destination address of the current transfer.Destination Address Register for Channels 0-1

Bit Range	Default	Access	Field Name and Description
31:0	0h	RW	DAR_LO (DAR_LO) Current Destination Address of DMA transfer. Updated after each destination transfer. The DINC field in the CTL_LO[n]: Control Register determines whether the address increments or is left unchanged on every destination transfer throughout the block transfer. When the channel is enabled (i.e. CH_EN is 1), the read back value will reflect the updated destination transfer addresses. However, when the channel is disabled, the original programmed value will be reflected when reading this register. It's important to notice the following: 1. Once the block transfer is in progress (i.e. when channel is enabled), the read-back value correlates with the OCP Write Address that one would see in an OCP tracker. 2. If the read to this register comes during a block transfer, the LAST DMA Write address sent on the OCP before the register read is what's reflected in the read-back value. 3. If the last DMA write was a burst write (i.e. burst length ) 1), the read-back value reflects the first address of the burst write since this is what gets sent on the OCP fabric. 4. If the read to the register occurred after the whole block got transferred, then the channel gets disabled and the returned value would be the original programmed value. 5. Since the read-back value is OCP based, only DW aligned addresses will be reflected (i.e. OCP Byte-Enable values would not be reflected) 6. Based on the above remarks, this value should be used as pseudo DMA write progress indicator when the channel is enabled and not an absolute one. Decrementing addresses are not supported

Bit Range

Default

Access

Field Name and Description

31:0

DAR_LO (DAR_LO)

Current Destination Address of DMA transfer.
Updated after each destination transfer. The DINC field in the CTL_LO[n]: Control
Register determines whether the address increments or is left unchanged on every
destination transfer throughout the block transfer. When the channel is enabled (i.e.
CH_EN is 1), the read back value will reflect the updated destination transfer addresses.
However, when the channel is disabled, the original programmed value will be reflected
when reading this register.
It's important to notice the following:
1. Once the block transfer is in progress (i.e. when channel is enabled), the read-back
value correlates with the OCP Write Address that one would see in an OCP tracker.
2. If the read to this register comes during a block transfer, the LAST DMA Write
address sent on the OCP before the register read is what's reflected in the read-back
value.
3. If the last DMA write was a burst write (i.e. burst length ) 1), the read-back value
reflects the first address of the burst write since this is what gets sent on the OCP fabric.
4. If the read to the register occurred after the whole block got transferred, then the
channel gets disabled and the returned value would be the original programmed value.
5. Since the read-back value is OCP based, only DW aligned addresses will be reflected
(i.e. OCP Byte-Enable values would not be reflected)
6. Based on the above remarks, this value should be used as pseudo DMA write
progress indicator when the channel is enabled and not an absolute one.
Decrementing addresses are not supported