eSPI IO Routing Enables for ESPI CS3 (ESPI_IORE_EXT[3]) – Offset 240 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

eSPI IO Routing Enables for ESPI CS3 (ESPI_IORE_EXT[3]) – Offset 240

Bit Range	Default	Access	Field Name and Description
31:15	0h	RO	Reserved (RSVD_31_15) Reserved.
14	0h	RW/V	Debug Port CS3# Routing Enable (DPRE) Enables routing of I/O locations 80h, 84h-86h, 88h, 8Ch-8Eh, 90h, 94h-96h, 98h, 9Ch-9Eh to eSPI CS3#. This field is only writeable if the eSPI CS3# is enabled and is RO when eSPI CS3# is disabled.
13	0h	RW/V	Microcontroller #2 CS3# Routing Enable (MRE2) Enables routing of I/O locations 4Eh and 4Fh to eSPI CS3#. This field is only writeable if the eSPI CS3# is enabled and is RO when eSPI CS3# is disabled.
12	0h	RW/V	SuperI/O CS3# Routing Enable (SRE) Enables routing of I/O locations 2Eh and 2Fh to eSPI CS3#. This field is only writeable if the eSPI CS3# is enabled and is RO when eSPI CS3# is disabled.
11	0h	RW/V	Microcontroller #1 CS3# Routing Enable (MRE1) Enables routing of I/O locations 62h and 66h to eSPI CS3#. This field is only writeable if the eSPI CS3# is enabled and is RO when eSPI CS3# is disabled.
10	0h	RW/V	Keyboard CS3# Routing Enable (KRE) Enables routing of the keyboard I/O locations 60h and 64h to eSPI CS3#. This field is only writeable if the eSPI CS3# is enabled and is RO when eSPI CS3# is disabled.
9	0h	RW/V	High Gameport CS3# Routing Enable (HGRE) Enables routing of the I/O locations 208h to 20Fh to eSPI CS3#. This field is only writeable if the eSPI CS3# is enabled and is RO when eSPI CS3# is disabled.
8	0h	RW/V	Low Gameport CS3# Routing Enable (LGRE) Enables routing of the I/O locations 200h to 207h to eSPI CS3#. This field is only writeable if the eSPI CS3# is enabled and is RO when eSPI CS3# is disabled.
7:4	0h	RO	Reserved (RSVD_7_4) Reserved
3	0h	RW/V	Floppy Drive CS3# Routing Enable (FDRE) Enables routing of the FDD range to eSPI CS3#. Range is selected by LIOD.FDE. This field is only writeable if the eSPI CS3# is enabled and is RO when eSPI CS3# is disabled.
2	0h	RW/V	Parallel Port CS3# Routing Enable (PPRE) Enables routing of the LPT range to eSPI CS3#. Range is selected by LIOD.LPT. This field is only writeable if the eSPI CS3# is enabled and is RO when eSPI CS3# is disabled.
1	0h	RW/V	Com Port B CS3# Routing Enable (CBRE) Enables routing of the COMB range to eSPI CS3#. Range is selected by LIOD.CB. This field is only writeable if the eSPI CS3# is enabled and is RO when eSPI CS3# is disabled.
0	0h	RW/V	Com Port A CS3# Routing Enable (CARE) Enables routing of the COMA range to eSPI CS3#. Range is selected by LIOD.CA. This field is only writeable if the eSPI CS3# is enabled and is RO when eSPI CS3# is disabled.