Event Ring Dequeue Pointer Low (ERDP_LO0) – Offset 2038 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

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xDCI PCI Configuration

Event Ring Dequeue Pointer Low (ERDP_LO0) – Offset 2038

There are 8 ERDP_LO registers.
x = 1, 2, ...,8

Bit Range	Default	Access	Field Name and Description
31:4	0h	RW	Event Ring Dequeue Pointer (ERDP) This field may be used by the xHC to accelerate checking the Event Ring full condition. This field is written with the low order 3 bits of the offset of the ERST entry which defines the Event Ring segment that Event Ring Dequeue Pointer resides in.
3	0h	RW/1C	Event Handler Busy (EHB) This flag shall be set to ‘1’ when the IP bit is set to ‘1’ and cleared to ‘0’ by software when the Dequeue Pointer register is written.
2:0	0h	RW	Dequeue ERST Segment Index (DESI) This field may be used by the xHC to accelerate checking the Event Ring full condition. This field is written with the low order 3 bits of the offset of the ERST entry which defines the Event Ring segment that Event Ring Dequeue Pointer resides in.

Bit Range

Default

Access

Field Name and Description

31:4

Event Ring Dequeue Pointer (ERDP)

This field may be used by the xHC to accelerate checking the Event Ring full condition. This field is written with the low order 3 bits of the offset of the ERST entry which defines the Event Ring segment that Event Ring Dequeue Pointer resides in.

RW/1C

Event Handler Busy (EHB)

This flag shall be set to ‘1’ when the IP bit is set to ‘1’ and cleared to ‘0’ by software when the Dequeue Pointer register is written.

2:0

Dequeue ERST Segment Index (DESI)

Event Ring Dequeue Pointer High (ERDP_HI0)

Event Ring Segment Table Base Address High (ERSTBA_HI0) Event Ring Dequeue Pointer High (ERDP_HI0)

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Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Event Ring Dequeue Pointer Low (ERDP_LO0) – Offset 2038