Flash Access Channel Error for eSPI First Device (FCERR_SLV0) – Offset 4040 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

Flash Access Channel Error for eSPI First Device (FCERR_SLV0) – Offset 4040

This register is used to determine how to log and report errors on the Flash Access channel, for both MAF and SAF configurations.

Bit Range	Default	Access	Field Name and Description
31:19	0h	RO	Reserved (RSVD) Reserved
18	1h	RO/V	SAF CAM Empty (SAFCAMEMPTY) Only valid in SAF mode. Will always read 1 otherwise. 0: SAF CAM is not empty - there are outstanding NP flash transactions to the eSPI device. 1: SAF CAM is empty - there are no outstanding NP flash transactions to the eSPI device.
17	0h	RW/1C/V	SAF Blocked (SAFBLK) Only valid in SAF mode. Will never be set to 1 by hardware otherwise. Set to 1 by hardware, when SAF NF Error Blocking Enable is set, when a NON_FATAL_ERROR response is received in response to a GET_FLASH_C. When this bit is set, the eSPI controller will not issue any additional transactions on the flash channel. Software must write a 1 to clear this bit.
16	0h	RW	SAF NF Error Blocking Enable (SAFNFEBLKEN) Only valid in SAF mode. Has no impact otherwise. 1: the flash channel will be blocked when a NON_FATAL_ERROR response is received in response to a GET_FLASH_C. 0: the flash channel will NOT be blocked when a NON_FATAL_ERROR response is received in response to a GET_FLASH_C.
15	0h	RO	Reserved (RSVD1) Reserved
14:13	0h	RW	Flash Access Channel Non-Fatal Error Reporting Enable (FCNFEE) 2'b00: Disable Non-Fatal Error Reporting 2'b01: Reserved 2'b10: Enable Non-Fatal Error Reporting as SERR (IOSF-SB Do_SErr message) 2'b11: Enable Non-Fatal Error Reporting as SMI (IOSF-SB Assert_SMI message) SERR enable is also qualified by PCCMD.SEE (Offset 04h) when PLTRST# is deasserted. SERR also sets PCSTS.SSE (Offset 06h) when PLTRST# is deasserted. SMI/SERR messages are not generated if the Host is in reset (PLTRST# asserted).
12	0h	RW/1C/V	Flash Access Channel Non-Fatal Error Status (FCNFES) This field is set by hardware if a Non-Fatal Error condition is detected on the Flash Access Channel. Software must clear this bit. 1'b0: No Non-Fatal Error detected 1'b1: Non-Fatal Error detected (FCNFEC has a non-zero value) Clearing this unlocks the FCNFEC field and triggers an IOSF-SB Deassert_SMI message if FCNFEE is set to SMI. Setting of this bit is independent of the enable to generate a SMI/SERR (FCNFEE).
11:8	0h	RO/V	Flash Access Channel Non-Fatal Error Cause (FCNFEC) 4'h0: No error 4'h1: Device Response Code: NONFATAL_ERROR received in response to GET_FLASH_NP, PUT_FLASH_C [for MAF accesses only] or GET_FLASH_C [for SAF accesses only]. 4'h2: Device Response Code: Unsuccessful Completion [for SAF accesses only] 4'h3: Unexpected completion received from device (i.e. completion without non-posted request or completion with invalid tag or completion with invalid length) [for SAF accesses only] 4'h4: Unsupported Cycle Type (w.r.t. Command) 4'h5: Device Response Code: NONFATAL_ERROR received in response to PUT_FLASH_NP [for SAF accesses only]. 4'h6: Unsupported Address (i.e., address > Flash linear address range) [for MAF accesses only] set to Flash Access Error 4'h7: Reserved 4'h8-4'hF: Reserved This field is updated after a Flash Access Channel transaction is completed if the FCNFES bit is not set
7	1h	RW	Master Attached Flash Request Priority (MAFRP) 1'b0: MAF Completion Requests are highest priority 1'b1: MAF Non-posted Requests are highest priority
6:5	0h	RW	Flash Access Channel Fatal Error Reporting Enable (FCFEE) 2'b00: Disable Fatal Error Reporting 2'b01: Reserved 2'b10: Enable Fatal Error Reporting as SERR (IOSF-SB Do_SErr message) 2'b11: Enable Fatal Error Reporting as SMI (IOSF-SB Assert_SMI message) SERR enable is also qualified by PCCMD.SEE (Offset 04h) when PLTRST# is deasserted. SERR also sets PCSTS.SSE (Offset 06h) when PLTRST# is deasserted. SMI/SERR messages are not generated if the Host is in reset (PLTRST# asserted).
4	0h	RW/1C/V	Flash Access Channel Fatal Error Status (FCFES) This field is set by hardware if a Fatal Error condition is detected on the Flash Access Channel. Software must clear this bit by writing a 1 to it. 1'b0: No Fatal Error detected 1'b1: Fatal Error Type 2 detected (FCFEC has a non-zero value) Clearing this unlocks the FCFEC field and triggers an IOSF-SB Deassert_SMI message if FCFEE is set to SMI. Setting of this bit is independent of the enable to generate a SMI/SERR (FCFEE).
3:0	0h	RO/V	Flash Access Channel Fatal Error Cause (FCFEC) 4'h0: No error 4'h1-4'h7: Reserved 4'h8: Malformed Device Response Payload: Payload length > Max Payload Size [Type 2] 4'h9: Malformed Device Response Payload: Read request size > Max Read Request Size [for MAF accesses only] [Type 2] 4'hA-4'hF: Reserved This field is updated after a Flash Access Channel transaction is completed if the FCFES bit is not set.