Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2
ID | Date | Version | Classification |
---|---|---|---|
834576 | 10/10/2024 | 001 | Public |
Frame Length Adjustment (FLADJ) – Offset 61
This feature is used to adjust any offset from the clock source that generates the clock that drives the SOF counter. When a new value is written into these six bits, the length of the frame is adjusted. Its initial programmed value is system dependent based on the accuracy of hardware USB clock and is initialized by system BIOS. This register should only be modified when the HChalted bit in the USBSTS register is a one. Changing value of this register while the host controller is operating yields undefined results.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
7 | 0h | RO | Reserved (RSVD)
|
6 | 1h | RO | No Frame Length Timing Capability (NO_FRAME_LENGTH_TIMING_CAP) This flag is set to 1 to indicate that the host controller does not support a programmable Frame Length Timing Value field. |
5:0 | 20h | RO | Frame Length Timing Value (FLTV) SOF micro-frame length) is equal to 59488 + value in this field. The default value is decimal 32 (20h), which gives a SOF cycle time of 60000. |