Function Configuration (FNCFG) – Offset 1e30 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Introduction
CNVi WiFi* PCI Configuration
eSPI PCI Configuration
eSPI PCR
GPIO Commumity 0
GPIO Commumity 1
GPIO Commumity 2
GPIO Commumity 3
GPIO Commumity 4
GPIO Commumity 5
GSPI Additional MMIO
GSPI DMA
GSPI MMIO
GSPI PCI Configuration
I2C Additional MMIO
I2C DMA
I2C MMIO
I3C / I2C / UART / GSPI PCR
I3C Additional MMIO
I3C DMA
I3C MMIO
I3C PCI Configuration
IDE-Redirect (IDE-R) PCI Configuration
Integrated GbE PCI Configuration
Integrated Sensor Hub (ISH) MMIO
Integrated Sensor Hub (ISH) PCI Configuration
Intel(R) Management Engine Interface (MEI) MMIO
Intel(R) Management Engine Interface (MEI) PCI Configuration
Intel® High Definition Audio MMIO
Intel® High Definition Audio PCI Configuration
Intergrated GbE MMIO
Keyboard and Text (KT) PCI Configuration
P2SB PCI Configuration
PCIe* PCI Configuration
PMC I/O Based
PMC MMIO
PMC PCI Configuration
PMC SSRAM PCI Configuration
RTC Index
RTC PCR
SATA ABAR
SATA AIDPBA
- AHCI Index Register (INDEX)
- AHCI Data Register (DATA)
SATA Initialization (SIR) Index
SATA MXPBA
- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
- MSI-X Pending Bit Array QW 1 (MXPQW0_DW1)
SATA MXTBA
SATA PCI Configuration
SATA Port 0 ABAR
SATA Port 1 ABAR
SATA Port 2 ABAR
SATA Port 3 ABAR
SATA Port 4 ABAR
SATA Port 5 ABAR
SATA Port 6 ABAR
SATA Port 7 ABAR
SMBus MMIO and I/O
SMBus PCI Configuration
SMBus PCR
SMBus TCO I/O
SPI MMIO
SPI PCI Configuration
THC MMIO Common
- Device Idle Control Register (THC_M_CMN_DEVIDLECTRL)
- THC LTR Control Register (THC_M_CMN_LTR_CTRL)
THC MMIO Port
THC PCI Configuration
UART Additional MMIO
UART DMA
UART MMIO
UART PCI Configuration
USB MMIO
USB PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration

Function Configuration (FNCFG) – Offset 1e30

Bit Range	Default	Access	Field Name and Description
31:7	0h	RO	Reserved (RSVD0) This is a Reserved Register
6	0h	RW	SRAM Retention Mode Disable (SRMD) Register is used to disable the SRAM retention mode capability of the L1 and L2 SRAMs.
5	1h	RW	Power Gating Disabled (PGD) When cleared, it allows power gating to take place per their associated enable and idle conditions.When set, it globally disables all power gating.
4	0h	RW	BIOS Configuration Lock Down (BCLD) When set, it indicates BIOS configuration is done and ready for operations.
3	1h	RW	Clock Gating Disabled (CGD) When cleared, it allows local/dynamic clock gating and trunk clock gating to take place per the associated enable and idle conditions.When set, it globally disables all clock gating.
2	0h	RW	DSP Subsystem Disable (DSPSD) When set, the DSP subsystem is disabled and all register accesses associated with DSP subsystem are treated as unsupported requests, and returns the UR response if it is a non-posted cycle. This bit does not affect cycles from IOSF Sideband Interface.
1	1h	RW	ACE IP as PCI Device (ACEPCID) When this bit is set to 1, the ACE IP appears as a PCI device to the software.When this bit is 0, the ACE IP appears as a PCI-Express device to the software.
0	0h	RW	ACE IP Disable (ACED) When set, the ACE IP (including DSP subsystem) is disabled and all register accesses are treated as unsupported requests, and returns the UR response if it is a non-posted cycle.This bit does not affect cycles from IOSF Sideband Interface.

Wall Clock Counter Alias (WALCLKA)

Power Transition Delay Control (PTDC) Wall Clock Counter Alias (WALCLKA)