General PM Configuration A (GEN_PMCON_A) – Offset 1020 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

General PM Configuration A (GEN_PMCON_A) – Offset 1020

Bit Range	Default	Access	Field Name and Description
31	0h	RO	Reserved
30	0h	RW	DC PHY Power Disable (DC_PP_DIS) This bit determines the Host software contribution to whether the LAN PHY remains powered in Sx/MOFF or DeepSx while on battery.
29	1h	RW	Deep-Sx PHY Power Disable (DSX_PP_DIS) This bit determines the Host software contribution to whether the LAN PHY remains powered in DeepSx. If this bit is cleared, for the PHY to be powered in deep-Sx state, SX_PP_EN must be set to 1.
28	0h	RW	After G3 PHY Power Enable (AG3_PP_EN) This bit determines the Host software contribution to whether the LAN PHY is powered up after exiting G3 (to either Sx/MOFF or DeepSx).
27	0h	RW	Sx PHY Power Enable (SX_PP_EN) This bit determines the Host software contribution to whether the LAN PHY remains powered in an Sx/MOFF state that was entered from S0 (rather than from G3).
26:25	0h	RO	Reserved
24	0h	RW/1C/V	Global Reset Status (GBL_RST_STS) This bit is set after a global reset (not G3 or DeepSx) occurs.
23	0h	RW	DRAM Initialization Scratchpad Bit (DISB) This bit does not effect hardware functionality in any way. It is provided as a scratchpad bit that is maintained through main power well resets and CF9h-initiated resets. BIOS is expected to set this bit prior to starting the DRAM initialization sequence and to clear this bit after completing the DRAM initialization sequence. BIOS can detect that a DRAM initialization sequence was interrupted by a reset by reading this bit during the boot sequence. If the bit is 1, then the DRAM initialization was interrupted. This bit is reset by the assertion of the RSMRST# pin.
22	0h	RO	Reserved
21	0h	RO/V	Memory Placed in Self-Refresh (MEM_SR) This bit will be set to 1 if DRAM should have remained powered and held in Self-Refresh through the last power state transition (i.e. the last time the system left S0). The scenarios where this should be the case are: - successful S3 entry & exit - successful Host partition reset without power cycle These scenarios both involve a handshake between the PCH and the CPU. The acknowledge from the CPU back to the PCH is assumed to imply that memory was successfully placed into Self-Refresh (the PCH has no way to verify whether that actually occurred). This bit will be cleared whenever the PCH begins a transition out of S0.
20:19	0h	RO	Reserved
18	0h	RW/1C/V	Minimum SLP_S4# Assertion Width Violation Status (MS4V) Hardware sets this bit when the SLP_S4# assertion width is less than the time programmed in the SLP_S4# Minimum Assertion Width field (D31.F0.A4h.5:4). The PCH begins the timer when SLP_S4# pin (including ME override logic) is asserted during S4/S5 entry, or when the RSMRST# input is deasserted during Primary well power-up. The status bit is cleared by software writing a 1 to the bit. Note that this bit is functional regardless of the value in the SLP_S4# Assertion Stretch Enable and the Disable SLP_X Stretching After SUS Power Failure bits. This bit is reset by the assertion of the RSMRST# pin, but can be set in some cases before the default value is readable.
17	0h	RO	Reserved
16	1h	RW/1C	SUS Well Power Failure (SUS_PWR_FLR) This bit is set to '1' whenever SUS well power is lost, as indicated by RSMRST# assertion. Software writes a 1 to this bit to clear it.
15	0h	RW	PME B0 S5 Disable (PME_B0_S5_DIS) When set to '1', this bit blocks wake events from PME_B0_STS in S5, regardless of the state of PME_B0_EN. When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = '1'. Wakes from power states other than S5 are not affected by this policy bit. The net effect of setting PME_B0_S5_DIS = '1' is described by the truth table below: Y = Wake N = Don't wake B0 = PME_B0_EN OV = WOL Enable Override B0/OV \| S1/S3/S4 \| S5 00 \| N \| N 01 \| N \| Y (LAN only) 11 \| Y (all PME B0 sources) \| Y (LAN only) 10 \| Y (all PME B0 sources) \| N This bit is cleared by the RTCRST# pin.
14	1h	RW/1C	PWR_FLR (PF) 1 = Indicates that the trickle current (from the main battery or trickle supply) was removed or failed. 0 = Indicates that the trickle current has not failed since the last time the bit was cleared. Software writes a 1 to this bit to clear it.
13	0h	RO	Reserved
12	0h	RW/L	Disable SLP_X Stretching After SUS Well Power Up (DIS_SLP_X_STRCH_SUS_UP) When this bit is set to 1, all SLP_* pin stretching is disabled when powering up after a SUS well power loss. When this bit is left at 0, SLP_* stretching will be performed after SUS power failure as enabled in various other fields. Note that if this bit is a 0, SLP_* stretch timers start on SUS well power up (the PCH has no ability to count stretch time while the primary well is powered down). Setting this bit can therefore prevent long delays after the primary power loss which may be common in mobile platforms and in manufacturing flow testing, while still allowing for the full power cycling during S3, S4 and S5 states. If the platform guarantees minimum SUS power down residence in other ways, an additional PCH-induced delay is not needed or wanted. Note: This policy bit has a different effect on SLP_SUS# stretching than on the other SLP_* pins, since SLP_SUS# is the control signal for one of the scenarios where SUS well power is lost (DeepSx). The effect of setting this bit to '1' on: - SLP_S3#, SLP_S4#, SLP_A# and SLP_LAN# stretching: disabled after any SUS power loss - SLP_SUS# stretching: disabled after G3, but no impact on DeepSx This field is not writable when the SLP_Sx# Stretching Policy Lock-Down bit is set. This bit is cleared by the RTCRST# pin.
11:10	0h	RW/L	SLP_S3# Minimum Assertion Width (SLP_S3_MIN_ASST_WDTH) This 2-bit value indicates the minimum assertion width of the SLP_S3# signal to guarantee that the Main power supplies have been fully power-cycled. This value may be modified per platform depending on power supply capacitance, board capacitance, power failure detection circuits, etc. Settings are: 00: 60 usec 01: 1 ms 10: 50 ms 11: 2 sec This field is not writable when the SLP_Sx# Stretching Policy Lock- Down bit is set. This bit is cleared by RSMRST#.
9	0h	RW/1C/V	Host Reset Status (HOST_RST_STS) This bit is set by hardware when a host partition reset (not a global reset, DeepSx, or G3) occurs. This bit is an optional tool to help BIOS determine when a host partition reset might have collided with a wake from a valid sleep state. A possible usage model would be to consult and then write a '1' to clear this bit during the boot flow before determining what action to take based on reading PM1_STS.WAK_STS = '1'. If HOST_RST_STS = '1' and/or GEN_PMCON_A.GBL_RST_STS = '1', the cold reset boot path could be followed rather than the resume path, regardless of the setting of WAK_STS. This bit does not affect PCH operation in any way, and can therefore be left set if BIOS chooses not to use it.
8	0h	RW/L	ESPI SMI Lock (ESPI_SMI_LOCK) When this bit is set, writes to the ESPI_SMI_EN bit will have no effect. Once the ESPI_SMI_LOCK bit is set, writes of 0 to ESPI_SMI_LOCK bit will have no effect (i.e. once set, this bit can only be cleared by RSMRST#).
7:6	0h	RW	SWSMI Rate Select (SWSMI_RATESEL) This 2-bit value indicates when the SWSMI timer will time out. Valid values are: 00 1.5ms +/- 0.6ms 01 16ms +/- 4ms 10 32ms +/- 4ms 11 64ms +/- 4ms These bits are not cleared by any type of reset except RTCRST#.
5:4	0h	RW/L	SLP_S4# Minimum Assertion Width (S4MAW) This 2-bit value indicates the minimum assertion width of the SLP_S4# signal to guarantee that the DRAMs have been safely power-cycled. This value may be modified per platform depending on DRAM types, power supply capacitance, etc. Valid values are: 11: 1 second 10: 2 seconds 01: 3 seconds 00: 4 seconds This value is used in two ways: 1. If the SLP_S4# assertion width is ever shorter than this time, a status bit (D31.F0.A2h.2) is set for BIOS to read when S0 is entered 2. If enabled by bit 3 in this register, the hardware will prevent the SLP_S4# signal from deasserting within this minimum time period after asserting. Note that the logic that measures this time is in the primary power well. Therefore, when leaving a G3 or DeepSx state, the minimum time is measured from the deassertion of the internal suspend well reset (unless the Disable SLP_X Stretching After SUS Power Failure bit is set). This field is not writable when the SLP_Sx# Stretching Policy Lock-Down bit is set. RTCRST# forces this field to the conservative default state (00b).
3	0h	RW/L	SLP_S4# Assertion Stretch Enable (S4ASE) When set to 1, the SLP_S4# pin (which includes the ME override logic) will minimally assert for the time specified in bits 5:4 of this register. This bit is provided so that all DIMMs in the system can deterministically detect a power-cycle event for proper initialization. Note that there are behavioral changes that may be noticeable to the end-user when this bit is set. Resume times from S4 and S5 and power-up times from G3 or DeepSx may be delayed by several seconds. Cases in which this feature may not be desirable and therefore keeping the bit cleared are: A customer decides the user confusion due to the hardware delay is a bigger issue than the potential DRAM issue A customer decides the software status bit solution is adequate A different DRAM type is used or the platform provides an external solution to solve the power-cycling issue Validation regressions are impacted by the delay (especially after RSMRST# deassertion) Avoid potential resume time WHQL violations This bit is not writable when the SLP_Sx# Stretching Policy Lock-Down bit is set. This bit is cleared by RTCRST#.
2:1	0h	RW	Period SMI Select (PER_SMI_SEL) Software sets these bits to control the rate at which the periodic SMI# is generated: 00 = 64 seconds (default) 01 = 32 seconds 10 = 16 seconds 11 = 8 seconds Tolerance for the timer is +/- 1 second.
0	0h	RW	AFTERG3_EN (AG3E) Determines what state to go to when power is reapplied after a power failure (G3 state). 0 = System will return to an S0 state (boot) after power is re-applied. 1 = System will return to the S5 state (except if it was in S4, in which case it will return to S4-like state). In the S5 state, the only enabled wake-up event is the Power Button or any enabled wake event that was preserved through the power failure. This bit is in the RTC well and is only cleared by RTCRST# assertion.