General Purpose Event 0 Enable [127:96] (GPE0_EN_127_96) – Offset 7c - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

General Purpose Event 0 Enable [127:96] (GPE0_EN_127_96) – Offset 7c

This register is symmetrical to the General Purpose Event 0 Status [127:96] Register.
Note that GPE0_STS bits 95:0 are claimed by the GPIO register block.

Bit Range	Default	Access	Field Name and Description
31:24	0h	RO	Reserved (RSVD) Reserved
23:20	0h	RO	Reserved (RSVD_1) Reserved
19	0h	RW	CPU Wake Enable (CPU_WAKE_EN) (CPU_WAKE_EN) Used to enable the setting of the CPU to PCH wake bit to generate wake/SMI#/SCI.
18	0h	RW	Wake Alarm Device Timer Enable (WADT_EN) Used to enable the setting of the WADT_STS bit to generate wake/SMI#/SCI.
17	0h	RW	USB Connection in/after DeepSx Enable (USB_CON_DSX_EN) Used to enable the setting of the USB_CON_DSX_STS bit to generate wake/SMI#/SCI.
16	0h	RW	GPIO[27] Enable (LANWAKE_EN) Used to enable the setting of the LANWAKE_STS bit to generate wake/SMI#/SCI. Host wake events from the PHY through LANWAKE cannot be disabled by clearing this bit.
15	0h	RW/V	GPIO Tier2 SCI EN (GPIO_TIER2_SCI_EN) Used to enable the setting of GPIO_TIER2_SCI_STS to generate wake/SCI#.
14	0h	RW/V	eSPI SCI Enable (ESPI_SCI_EN) Used to enable the setting of the ESPI_SCI_STS bit to generate a SCI.
13	0h	RW/V	PME_B0 Enable (PME_B0_EN) Enables the setting of the PME_B0_STS bit to generate a wake event and/or an SCI or SMI#.
12	0h	RW/V	ME SCI Enable (ME_SCI_EN) Used to enable the setting of the ME_SCI_STS bit to generate a SCI.
11	0h	RW/V	Power Management Event Enable (PME_EN) Enables the setting of the PME_STS to generate a wake event and/or an SCI.
10	0h	RW/V	Reserved (BATLOW_EN)
9	0h	RW/V	PCI Express Enable (PCI_EXP_EN) Enables PCH to cause an SCI when PCI_EXP_STS bit is set. This is used to allow the PCI Express ports, to cause an SCI due to wake/PME events.
8	0h	RW/V	ISH Enable (ISH_EN) When ISH_EN and ISH_STS are both set, a Wake event will occur. If ISH_EN is not set, then when ISH_STS is set, no Wake event will occur.
7	0h	RO	Reserved (RSVD2)
6	0h	RW/V	TCOSCI Enable (TCOSCI_EN) When TCOSCI_EN and TCOSCI_STS are both set, an SCI will be generated.
5	0h	RO	Reserved (RSVD1) Reserved
4	0h	RW	Thermal SCI Enable (THERM_EN) When THERM_EN and THERM_SCI_STS are both set, an SCI will be generated.
3	0h	RO	Reserved (RSVD_3) Reserved
2	0h	RW/V	Software GPE Enable (SWGPE_EN) This bit, when set to 1, enables the SW GPE function. If SWGPE_CTRL is written to a 1, hardware will set SWGPE_STS (acts as a level input) If SWGPE_STS, SWGPE_EN, and SCI_EN are all 1's, an SCI will be generated If SWGPE_STS = 1, SWGPE_EN = 1, SCI_EN = 0, and GBL_SMI_EN = 1 then an SMI# will be generated
1	0h	RW/V	Hot Plug Enable (HOT_PLUG_EN) Enables PCH to cause an SCI when the HOT_PLUG_STS bit is set. This is used to allow the PCI Express ports to cause an SCI due to hot-plug events. (The following events cause HOT_PLUG_STS bit to set Assert_GPE message received from any of the PCI_E ports in PCH Assert_HPGPE message received from any of the PCI_E ports in PCH Assert_GPE message received downstream from the processor Assert_HPGPE message received downstream from the processor
0	0h	RO	Reserved