General Purpose Event 0 Status [127:96] (GPE0_STS_127_96) – Offset 6c - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

General Purpose Event 0 Status [127:96] (GPE0_STS_127_96) – Offset 6c

This register is symmetrical to the General Purpose Event 0 Enable [127:96] Register. Unless indicated otherwise below, if the corresponding _EN bit is set, then when the STS bit get set, the processor will generate a Wake Event. Once back in an S0 state (or if already in an S0 state when the event occurs), the processor will also generate an SCI if the SCI_EN bit is set, or an SMI# if the SCI_EN bit is not set and GBL_SMI_EN is set.
Note that GPE0_STS bits 95:0 are claimed by the GPIO register block.

Bit Range	Default	Access	Field Name and Description
31:24	0h	RO	Reserved (RSVD) Reserved
23:20	0h	RO	Reserved (RSVD_1) Reserved
19	0h	RW/1C/V	CPU Wake Status (CPU_WAKE_STS) (CPU_WAKE_STS) This bit is set when the CPU to PCH wake pin asserts.
18	0h	RW/1C/V	Wake Alarm Device Timer Status (WADT_STS) This bit is set whenever the any of the wake alarm device timers signal a timer expiration.
17	0h	RW/1C/V	USB Connection in/after DeepSx Status (USB_CON_DSX_STS) This bit is set when a connection event occurs on any unmasked USB port while in DeepSx or while in Sx immediately after DeepSx. Note: Because this status bit is only set during DeepSx exit or while in Sx after DeepSx, SMI/SCI generation will only occur immediately as the platform enters S0. The event cannot occur and the bit cannot be set after the platform reaches S0. Hence, the event cannot generate an SMI/SCI after the platform reach S0.
16	0h	RO	Reserved
15	0h	RW/1C/V	GPIO Tier2 SCI Status (GPIO_TIER2_SCI_STS) This bit is a logical OR of sci_wake from tier 2 GPIO's.
14	0h	RW/1C/V	eSPI SCI Status (ESPI_SCI_STS) This bit will be set when an agent attached to eSPI is requesting an SCI. Note: This source is not able to cause a wake event.
13	0h	RW/1C/V	Power Management Event Bus 0 Status (PME_B0_STS) This bit will be set to 1 by the Intel PCH when any internal device with PCI Power Management capabilities on bus 0 asserts the equivalent of the PME# signal. Additionally, if the PME_B0_EN and SCI_EN bits are set, and the system is in an S0 state, then the setting of the PME_B0_STS bit will generate an SCI (or SMI# if SCI_EN is not set). If the PME_B0_EN bit is set, and the system is in an S1-S4 state (or S5 state due to SLP_TYP and SLP_EN), then the setting of the PME_B0_STS bit will generate a wake event. If the system is in an S5 state due to power button override, then the PME_B0_STS bit will not cause a wake event or SCI. This bit is cleared by a software write of '1'. Internal devices which can set this bit: - Integrated LAN - HD Audio/Audio DSP - SATA - XHCI - ME Maskable Host Wake
12	0h	RW/1C/V	ME SCI Status (ME_SCI_STS) This bit will be set when ME is requesting an SCI. Software must clear the ME source of the SCI before clearing this bit. Note: This source is not able to cause a wake event.
11	0h	RW/1C/V	Power Management Event Status (PME_STS) This bit will be set to 1 by hardware when the PME# signal goes active. Additionally, if the PME_EN and SCI_EN bits are set, and system is in an S0 state, then the setting of the PME_STS bit will generate an SCI (or SMI# if SCI_EN is not set). If the PME_EN bit is set, and the system is in an S1-S4 state (or S5 state due to SLP_TYP and SLP_EN), then the setting of the PME_STS bit will generate a wake event. If the system is in an S5 state due to power button override, then PME_STS will not cause a wake event or SCI. This bit is cleared by writing a 1 to this bit position.
10	0h	RW/1C/V	Reserved (BATLOW_STS)
9	0h	RW/1C/V	PCI Express Status (PCI_EXP_STS) This bit will be set to 1 by hardware to indicate that: The PME event message was received on one or more of the PCI-Express Ports An Assert PMEGPE message received from the processor Note: The PCI WAKE# pin and the PCI-Express Beacons have no impact on this bit. Software attempts to clear this bit by writing a 1 to this bit position. If the PCI_EXP_STS bit went active due to an Assert PMEGPE message, then a Deassert PMEGPE message must be received prior to the software write in order for the bit to be cleared. If the bit is not cleared and the corresponding PCI_EXP_EN bit is set, the leveltriggered SCI will remain active.
8	0h	RW/1C/V	ISH Status (ISH_STS) This bit will be set to1 by hardware when the ISH# input signal goes active. This bit can be reset by writing a 1 to this bit position.
7	0h	RW/1C/V	SMBus Wake Status (SMB_WAK_STS) This bit is set to 1 by the hardware to indicate that the wake event was caused by the SMBus logic. This could be due to either the SMBus TCO unit receiving a message or the SMBALERT# signal going active. NOTES: 1. The SMBus controller will independently cause an SMI# so this bit does not need to do so (unlike the other bits in this register). 2. This bit is set by the SMBus TCO command 01h (Wake/SMI#) even when the system is in the S0 state. Therefore, to avoid an instant wake on subsequent transitions to sleep states, software must clear this bit after each reception of the Wake/SMI# command or just prior to entering the sleep state. 3. The SMBALERT_STS bit (SMBus I/O Offset 00h:bit 5) should be cleared by software before clearing this bit. This bit is reset by RSMRST# assertion.
6	0h	RW/1C/V	TCOSCI Status (TCOSCI_STS) This bit will be set to 1 by hardware when the TCO logic or Thermal Sensor logic causes an SCI. This bit can be reset by writing a one to this bit position.
5	0h	RO	Reserved (RSVD_2) Reserved
4	0h	RW/1C/V	Thermal SCI Status (THERM_SCI_STS) This bit will be set to 1 by hardware when the firmware sets the DRV_THERM_SMI_SCI_STS.DRV_SCI_STS. This bit can be cleared by writing a one to this bit position.
3	0h	RW/1C/V	eSPI Unconditional Wake Status (ESPIUWAK_STS) This bit is set to 1 by hardware upon reception of an unconditional wake message from eSPI
2	0h	RW/1C/V	Software GPE Status (SWGPE_STS) The SWGPE_CTRL bit (bit 1 of GPE_CTRL reg) acts as a level input to this bit.
1	0h	RW/1C/V	Hot Plug Status (HOT_PLUG_STS) This bit is set to 1 by hardware when a PCI-Express hotplug event occurs. This will cause an SCI if the HOT_PLUG_EN and SCI_EN bits are set. This bit is cleared by writing a 1 to this bit position. The following events cause this bit to set Assert_GPE message received from any of the PCI_E ports in PCH Assert_HPGPE message received from any of the PCI_E ports in PCH Assert_GPE message received downstream from the processor Assert_HPGPE message received downstream from the processor
0	0h	RO	Reserved