Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2
ID | Date | Version | Classification |
---|---|---|---|
834576 | 10/10/2024 | 001 | Public |
General Purpose Event 0 Status [31:0] (GPE0_STS_31_0) – Offset 60
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:0 | 0h | RW/1C/V | General Purpose Event 0 Status [31:0] (GPE0_STS_31_0) These bits are set any time the corresponding GPIO is setup as an input and the corresponding GPIO signal is high (or low if the corresponding RXINV bit is set). If the corresponding enable bit is set in the GPE0_EN_31_0 register, then when the GPE0_STS_31_0 bit is set: |