General Purpose Event 0 Status [63:32] (GPE0_STS_63_32) – Offset 64 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

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General Purpose Event 0 Status [63:32] (GPE0_STS_63_32) – Offset 64

Bit Range	Default	Access	Field Name and Description
31:0	0h	RW/1C/V	General Purpose Event 0 Status [63:32] (GPE0_STS_63_32) These bits are set any time the corresponding GPIO is setup as an input and the corresponding GPIO signal is high (or low if the corresponding RXINV bit is set). If the corresponding enable bit is set in the GPE0_EN_63_32 register, then when the GPE0_STS_63_32 bit is set: - If system is in an S3-S5 state, the event will also wake the system. - If system is in an S0 state (or upon waking back to S0), an SCI will be caused, depending on the GPIROUTSCI bit for the corresponding GPI. These bits are sticky bits and are cleared by writing a 1 back to this bit position. Note: The GPP group mapped to this GPE0_STS_63_32 is configured via GPIO_CFG.DW1 and MISCCFG.DW1. Both GPIO_CFG.DW1 and MISCCFG.DW1 must be programmed to the same GPIO group.

Bit Range

Default

Access

Field Name and Description

31:0

RW/1C/V

General Purpose Event 0 Status [63:32] (GPE0_STS_63_32)

These bits are set any time the corresponding GPIO is setup as an input and the corresponding GPIO signal is high (or low if the corresponding RXINV bit is set). If the corresponding enable bit is set in the GPE0_EN_63_32 register, then when the GPE0_STS_63_32 bit is set:
- If system is in an S3-S5 state, the event will also wake the system.
- If system is in an S0 state (or upon waking back to S0), an SCI will be caused, depending on the GPIROUTSCI bit for the corresponding GPI. These bits are sticky bits and are cleared by writing a 1 back to this bit position.
Note: The GPP group mapped to this GPE0_STS_63_32 is configured via GPIO_CFG.DW1 and MISCCFG.DW1. Both GPIO_CFG.DW1 and MISCCFG.DW1 must be programmed to the same GPIO group.

General Purpose Event 0 Status [95:64] (GPE0_STS_95_64)

General Purpose Event 0 Status [31:0] (GPE0_STS_31_0) General Purpose Event 0 Status [95:64] (GPE0_STS_95_64)