General Purpose Event 1 Enable [63:32] (GPE1_EN_63_32) – Offset 20 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

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General Purpose Event 1 Enable [63:32] (GPE1_EN_63_32) – Offset 20

Enables for interrupts for GPE1_STS_63_32

Bit Range	Default	Access	Field Name and Description
31:8	0h	RO	Reserved
7	0h	RW/V	IOE Hot Plug Enable (IOE_HOT_PLUG_EN) Enables PCH to cause an SCI when the IOE_HOT_PLUG_STS bit is set. This is used to allow the PCI Express ports to cause an SCI due to hot-plug events.
6	0h	RO	Reserved
5	0h	RW/V	SPF Hot Plug Enable (SPF_HOT_PLUG_EN) Enables PCH to cause an SCI when the SPF_HOT_PLUG_STS bit is set. This is used to allow the PCI Express ports to cause an SCI due to hot-plug events.
4	0h	RW/V	SPE Hot Plug Enable (SPE_HOT_PLUG_EN) Enables PCH to cause an SCI when the SPE_HOT_PLUG_STS bit is set. This is used to allow the PCI Express ports to cause an SCI due to hot-plug events.
3	0h	RW/V	SPD Hot Plug Enable (SPD_HOT_PLUG_EN) Enables PCH to cause an SCI when the SPD_HOT_PLUG_STS bit is set. This is used to allow the PCI Express ports to cause an SCI due to hot-plug events.
2	0h	RW/V	SPC Hot Plug Enable (SPC_HOT_PLUG_EN) Enables PCH to cause an SCI when the SPC_HOT_PLUG_STS bit is set. This is used to allow the PCI Express ports to cause an SCI due to hot-plug events.
1	0h	RW/V	SPB Hot Plug Enable (SPB_HOT_PLUG_EN) Enables PCH to cause an SCI when the SPB_HOT_PLUG_STS bit is set. This is used to allow the PCI Express ports to cause an SCI due to hot-plug events.
0	0h	RW/V	SPA Hot Plug Enable (SPA_HOT_PLUG_EN) Enables PCH to cause an SCI when the SPA_HOT_PLUG_STS bit is set. This is used to allow the PCI Express ports to cause an SCI due to hot-plug events.

General Purpose Event 1 Enable [63:32] (GPE1_EN_95_64)

General Purpose Event 1 Enable [31:0] (GPE1_EN_31_0) General Purpose Event 1 Enable [63:32] (GPE1_EN_95_64)

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Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

General Purpose Event 1 Enable [63:32] (GPE1_EN_63_32) – Offset 20