Global Bus Configuration 0 (GSBUSCFG0) – Offset c100 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

Global Bus Configuration 0 (GSBUSCFG0) – Offset c100

Bit Range	Default	Access	Field Name and Description
31:12	0h	RO	Reserved
11	0h	RW	Data Access is Big-Endian (DATBIGEND) This bit controls the endian modefor data accesses. 0: Little-endian (default) 1: Big-endian In big-endian mode, DMAaccess (both read and write) for packet data will utilize a Byte Invariant BigEndianmode. Note: Since AXI requires byte invariant endianness, settingDescBigend and DatBigEnd to one causes an address invariant transform to be applied, which is not appropriate. Henceforth an AXI master (DWC_USB3_MBUS_TYPE=1), this bit must be set to zero.
10:8	0h	RO	Reserved
7	0h	RW	INCR256 Burst Type Enable (INCR256BRSTENA) if software set this bit to "1", the master uses INCR to do the 256-beat burst
6	0h	RW	INCR128 Burst Type Enable (INCR128BRSTENA) if software set this bit to "1", the master uses INCR to do the 128-beat burst
5	0h	RW	INCR64 Burst Type Enable (INCR64BRSTENA) if software set this bit to "1", the master uses INCR to do the 64-beat burst
4	0h	RW	INCR32 Burst Type Enable (INCR32BRSTENA) if software set this bit to "1", the master uses INCR to do the 32-beat burst
3	0h	RW	INCR16 Burst Type Enable (INCR16BRSTENA) if software set this bit to "1", the master uses INCR to do the 16-beat burst
2	1h	RW	INCR8 Burst Type Enable (INCR8BRSTENA) if software set this bit to "1", the master uses INCR to do the 8-beat burst
1	1h	RW	INCR4 Burst Type Enable (INCR4BRSTENA) When this bit is enabled the controller is allowed to do bursts of beat length 1, 2, 3, and 4
0	0h	RW	Undefined Length INCR Burst Type Enable (INCRBRSTENA) When enabled, this has higher priority than other burst types. For the AHB configuration. if this bit is set to 1, AHB master tries to do only one INCR burst for each transfer unless it has to break it at a 1Kbyte boundary. If this bit is set to 0, the AHB master may still use INCR burst type at the beginning and end bursts of transfers to align the address. The middle bursts are INCR4/8/16, depending when the type is enabled.