Global Core Control (GCTL) – Offset c110 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

Global Core Control (GCTL) – Offset c110

Bit Range	Default	Access	Field Name and Description
31:19	0h	RO	Reserved
18	0h	RW	Master Filter Bypass (MASTERFILTBYPASS) When this bit is set to 1'b1, irrespective ofthe parameter DWC_USB3_EN_BUS_FILTERS chosen, all the filters in the DWC_usb3_filter module will be bypassed. The double synchronizers to mac_clk preceding the filters will also be bypassed. For enabling the filters, this bit should be1'b0.
17	0h	RO	Reserved
16	0h	RW	U2RSTECN (U2RSTECN) The super speed connection fails during POLL or LMP exchange, thedevice connects at non-SS mode. If this bit is set, then device attempts three moretimes to connect at SS, even if it previously failed to operate in SS mode.
15:14	0h	RW	FRMSCLDWN (FRMSCLDWN) This field scales down device view of a SOF/USOF/ITP duration. For SS/HS mode: 2'h3: implements interval to be 15. 625 us 2'h2: implementsinterval to be 31.25 us 2'h1: implements interval to be 62.5 us 2'h0: implements interval to be125us For FS mode, the scale-down value is multiplied by 8.
13:12	2h	RW	Port Capability Direction (PRTCAPDIR) 2’b01: Reserved 2’b10: for Device configurations 2’b11: Reserved
11	0h	RW	Core Soft Reset (CORESOFTRESET) 1b0 - No soft reset 1b1 - Soft reset
10:4	0h	RO	Reserved
3	0h	RW	Diable Scrambling (DISSCRAMBLE) Transmit request to Link Partner on next transition to Recovery or Polling
2	0h	RO	Reserved
1	0h	RW	Global Hibernation Enable (GblHibernationEn) This bit enables hibernation at the global level. If hibernation is not enabled via this bit, the PMU immediately accepts the D0->D3 and D3->D0 power state change requests, but does not save or restore any core state. In addition, the PMUs will never drive the PHY interfaces and let the core continue to drive the PHY interfaces.
0	0h	RW	Disable Clock Gating (DSBLCLKGTNG) When this bit is set to 1 and the core is in Low Power mode, internal clock gating is disabled.You can set this bit to 1’b1 after Power On Rese