Global Rx Threshold Control (GRXTHRCFG) – Offset c10c - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Introduction
CNVi WiFi* PCI Configuration
eSPI PCI Configuration
eSPI PCR
GPIO Commumity 0
GPIO Commumity 1
GPIO Commumity 2
GPIO Commumity 3
GPIO Commumity 4
GPIO Commumity 5
GSPI Additional MMIO
GSPI DMA
GSPI MMIO
GSPI PCI Configuration
I2C Additional MMIO
I2C DMA
I2C MMIO
I3C / I2C / UART / GSPI PCR
I3C Additional MMIO
I3C DMA
I3C MMIO
I3C PCI Configuration
IDE-Redirect (IDE-R) PCI Configuration
Integrated GbE PCI Configuration
Integrated Sensor Hub (ISH) MMIO
Integrated Sensor Hub (ISH) PCI Configuration
Intel(R) Management Engine Interface (MEI) MMIO
Intel(R) Management Engine Interface (MEI) PCI Configuration
Intel® High Definition Audio MMIO
Intel® High Definition Audio PCI Configuration
Intergrated GbE MMIO
Keyboard and Text (KT) PCI Configuration
P2SB PCI Configuration
PCIe* PCI Configuration
PMC I/O Based
PMC MMIO
PMC PCI Configuration
PMC SSRAM PCI Configuration
RTC Index
RTC PCR
SATA ABAR
SATA AIDPBA
- AHCI Index Register (INDEX)
- AHCI Data Register (DATA)
SATA Initialization (SIR) Index
SATA MXPBA
- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
- MSI-X Pending Bit Array QW 1 (MXPQW0_DW1)
SATA MXTBA
SATA PCI Configuration
SATA Port 0 ABAR
SATA Port 1 ABAR
SATA Port 2 ABAR
SATA Port 3 ABAR
SATA Port 4 ABAR
SATA Port 5 ABAR
SATA Port 6 ABAR
SATA Port 7 ABAR
SMBus MMIO and I/O
SMBus PCI Configuration
SMBus PCR
SMBus TCO I/O
SPI MMIO
SPI PCI Configuration
THC MMIO Common
- Device Idle Control Register (THC_M_CMN_DEVIDLECTRL)
- THC LTR Control Register (THC_M_CMN_LTR_CTRL)
THC MMIO Port
THC PCI Configuration
UART Additional MMIO
UART DMA
UART MMIO
UART PCI Configuration
USB MMIO
USB PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration

Global Rx Threshold Control (GRXTHRCFG) – Offset c10c

Bit Range	Default	Access	Field Name and Description
31:30	0h	RO	Reserved
29	1h	RW	USB ReceivePacket Count Enable (USBRxPktCntSel) This field enables/disables theUSB reception multi-packet thresholding: 0: The core can only start reception on theUSB when the RX FIFO has space for at least one packet. 1: The core can only startreception on the USB when the RX FIFO has space for at least USBRxPktCnt amount ofpackets. This mode is only valid in the host mode. It is only used for SuperSpeed.
28	0h	RO	Reserved
27:24	4h	RW	USB Receive Packet Count (USBRxPktCnt) This field specifies space (in number ofpackets) that must be available in the RX FIFO before the core can start the corresponding USB RX transaction (burst). This field is only valid when the USB ReceivePacket Count Enable field is set to one. The valid values are from 1 to 15.
23:19	8h	RW	USB Maximum Rx Burst Size (USBMaxRxBurstSize) This field is only valid whenUSBRxPktCntSel is one. This field specifies the Maximum Bulk IN burst the coreshould do. When the system bus is slower than the USB, RX FIFO can overrun during along burst. User can program a smaller value to this field to limit the RX burst size thatthe core can do. It only applies to SS Bulk, Isochronous, and Interrupt IN endpoints inthe host mode. Valid values are from 1 to 16.
18:0	0h	RO	Reserved

Global Core Control (GCTL)

Global Tx Threshold Control (GTXTHRCFG) Global Core Control (GCTL)

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Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Global Rx Threshold Control (GRXTHRCFG) – Offset c10c