GPI General Purpose Events Enable (GPI_GPE_EN_GPP_J_0) – Offset 268 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

GPI General Purpose Events Enable (GPI_GPE_EN_GPP_J_0) – Offset 268

Bit Range	Default	Access	Field Name and Description
31:17	0h	RO	Reserved
16	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_GPP_J_16) same description as bit 0.
15	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_GPP_J_15) same description as bit 0.
14	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_GPP_J_14) same description as bit 0.
13	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_GPP_J_13) same description as bit 0.
12	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_GPP_J_12) same description as bit 0.
11	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_GPP_J_11) same description as bit 0.
10	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_GPP_J_10) same description as bit 0.
9	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_GPP_J_9) same description as bit 0.
8	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_GPP_J_8) same description as bit 0.
7	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_GPP_J_7) same description as bit 0.
6	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_GPP_J_6) same description as bit 0.
5	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_GPP_J_5) same description as bit 0.
4	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_GPP_J_4) same description as bit 0.
3	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_GPP_J_3) same description as bit 0.
2	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_GPP_J_2) same description as bit 0.
1	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_GPP_J_1) same description as bit 0.
0	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_GPP_J_0) This bit is used to enable/disable the generation of GPE to cause SCI and/or wake when the corresponding GPI_GPE_STS bit is set. 0 = disable GPE generation 1 = enable GPE generation Note: The pad must also be routed for GPE functionality in order for GPE to be generated, i.e. the corresponding GPIRoutSCI must be set to '1'.