GPI General Purpose Events Enable (GPI_GPE_EN_GPP_R_0) – Offset 264 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

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xDCI PCI Configuration

GPI General Purpose Events Enable (GPI_GPE_EN_GPP_R_0) – Offset 264

Bit Range	Default	Access	Field Name and Description
31:13	0h	RO	Reserved
12	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_GPP_R_12) same description as bit 0.
11	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_GPP_R_11) same description as bit 0.
10	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_GPP_R_10) same description as bit 0.
9	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_GPP_R_9) same description as bit 0.
8	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_GPP_R_8) same description as bit 0.
7	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_GPP_R_7) same description as bit 0.
6	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_GPP_R_6) same description as bit 0.
5	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_GPP_R_5) same description as bit 0.
4	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_GPP_R_4) same description as bit 0.
3	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_GPP_R_3) same description as bit 0.
2	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_GPP_R_2) same description as bit 0.
1	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_GPP_R_1) same description as bit 0.
0	0h	RW	GPI General Purpose Events Enable (GPI_GPE_EN_GPP_R_0) This bit is used to enable/disable the generation of GPE to cause SCI and/or wake when the corresponding GPI_GPE_STS bit is set. 0 = disable GPE generation 1 = enable GPE generation Note: The pad must also be routed for GPE functionality in order for GPE to be generated, i.e. the corresponding GPIRoutSCI must be set to '1'.

GPI General Purpose Events Enable (GPI_GPE_EN_GPP_J_0)

GPI General Purpose Events Enable (GPI_GPE_EN_GPP_D_0) GPI General Purpose Events Enable (GPI_GPE_EN_GPP_J_0)