GPI General Purpose Events Status (GPI_GPE_STS_GPP_B_0) – Offset 248 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

GPI General Purpose Events Status (GPI_GPE_STS_GPP_B_0) – Offset 248

Refer to Register Field for detail

Bit Range	Default	Access	Field Name and Description
31:22	0h	RO	Reserved (RSVD_0) Reserved
21	0h	RW/1C/V	GPI General Purpose Events Status (GPI_GPE_STS_GPP_B_21) Same description as bit 0.
20	0h	RW/1C/V	GPI General Purpose Events Status (GPI_GPE_STS_GPP_B_20) Same description as bit 0.
19	0h	RW/1C/V	GPI General Purpose Events Status (GPI_GPE_STS_GPP_B_19) Same description as bit 0.
18	0h	RW/1C/V	GPI General Purpose Events Status (GPI_GPE_STS_GPP_B_18) Same description as bit 0.
17	0h	RW/1C/V	GPI General Purpose Events Status (GPI_GPE_STS_GPP_B_17) Same description as bit 0.
16	0h	RW/1C/V	GPI General Purpose Events Status (GPI_GPE_STS_GPP_B_16) Same description as bit 0.
15	0h	RW/1C/V	GPI General Purpose Events Status (GPI_GPE_STS_GPP_B_15) Same description as bit 0.
14	0h	RW/1C/V	GPI General Purpose Events Status (GPI_GPE_STS_GPP_B_14) Same description as bit 0.
13	0h	RW/1C/V	GPI General Purpose Events Status (GPI_GPE_STS_GPP_B_13) Same description as bit 0.
12	0h	RW/1C/V	GPI General Purpose Events Status (GPI_GPE_STS_GPP_B_12) Same description as bit 0.
11	0h	RW/1C/V	GPI General Purpose Events Status (GPI_GPE_STS_GPP_B_11) Same description as bit 0.
10	0h	RW/1C/V	GPI General Purpose Events Status (GPI_GPE_STS_GPP_B_10) Same description as bit 0.
9	0h	RW/1C/V	GPI General Purpose Events Status (GPI_GPE_STS_GPP_B_9) Same description as bit 0.
8	0h	RW/1C/V	GPI General Purpose Events Status (GPI_GPE_STS_GPP_B_8) Same description as bit 0.
7	0h	RW/1C/V	GPI General Purpose Events Status (GPI_GPE_STS_GPP_B_7) Same description as bit 0.
6	0h	RW/1C/V	GPI General Purpose Events Status (GPI_GPE_STS_GPP_B_6) Same description as bit 0.
5	0h	RW/1C/V	GPI General Purpose Events Status (GPI_GPE_STS_GPP_B_5) Same description as bit 0.
4	0h	RW/1C/V	GPI General Purpose Events Status (GPI_GPE_STS_GPP_B_4) Same description as bit 0.
3	0h	RW/1C/V	GPI General Purpose Events Status (GPI_GPE_STS_GPP_B_3) Same description as bit 0.
2	0h	RW/1C/V	GPI General Purpose Events Status (GPI_GPE_STS_GPP_B_2) Same description as bit 0.
1	0h	RW/1C/V	GPI General Purpose Events Status (GPI_GPE_STS_GPP_B_1) Same description as bit 0.
0	0h	RW/1C/V	GPI General Purpose Events Status (GPI_GPE_STS_GPP_B_0) These bits are set any time the corresponding GPIO pad is set up as an input, under host ownership and the corresponding GPIO signal is high (or low if the corresponding RXINV bit is set). If the corresponding enable bit is set in the GPI_GPE_EN register, then when the GPI_GPE_STS[i] bit is set: - If the system is in an S3-S5 state, the event will also wake the system. - If the system is in an S0 state (or upon waking back to an S0 state), an SCI will be caused, depending on the GPIRoutSCI bit for the corresponding pad. These bits are sticky bits and are cleared by writing a 1 back to this bit position. The state of GPI_GPE_EN does not prevent the setting of GPI_GPE_STS.