GPI Interrupt Enable (GPI_IE_DSW_0) – Offset 220 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

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GPIO Commumity 5
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xDCI MMIO Device
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xDCI PCI Configuration

GPI Interrupt Enable (GPI_IE_DSW_0) – Offset 220

Refer to Register Field for detail

Bit Range	Default	Access	Field Name and Description
31:17	0h	RO	Reserved (RSVD_0) Reserved
16:13	0h	RO	Reserved
12	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPD_12) Same description as bit 0.
11	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPD_11) Same description as bit 0.
10	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPD_10) Same description as bit 0.
9	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPD_9) Same description as bit 0.
8	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPD_8) Same description as bit 0.
7	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPD_7) Same description as bit 0.
6	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPD_6) Same description as bit 0.
5	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPD_5) Same description as bit 0.
4	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPD_4) Same description as bit 0.
3	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPD_3) Same description as bit 0.
2	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPD_2) Same description as bit 0.
1	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPD_1) Same description as bit 0.
0	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPD_0) This bit is used to enable/disable the generation of APIC interrupt when the corresponding GPI_INT_STS bit is set. 0 = disable interrupt generation 1 = enable interrupt generation Refer to GPI_IRQ_ROUTE for host GPIO Driver Mode interrupt routing.

GPI General Purpose Events Status (GPI_GPE_STS_DSW_0)

GPI Interrupt Status (GPI_IS_DSW_0) GPI General Purpose Events Status (GPI_GPE_STS_DSW_0)