GPI Interrupt Enable (GPI_IE_GPP_F_0) – Offset 22c - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

GPI Interrupt Enable (GPI_IE_GPP_F_0) – Offset 22c

Bit Range	Default	Access	Field Name and Description
31:24	0h	RO	Reserved (RSVD_0) Reserved
23	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPP_F_23) Same description as bit 0.
22	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPP_F_22) Same description as bit 0.
21	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPP_F_21) Same description as bit 0.
20	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPP_F_20) Same description as bit 0.
19	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPP_F_19) Same description as bit 0.
18	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPP_F_18) Same description as bit 0.
17	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPP_F_17) Same description as bit 0.
16	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPP_F_16) Same description as bit 0.
15	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPP_F_15) Same description as bit 0.
14	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPP_F_14) Same description as bit 0.
13	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPP_F_13) Same description as bit 0.
12	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPP_F_12) Same description as bit 0.
11	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPP_F_11) Same description as bit 0.
10	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPP_F_10) Same description as bit 0.
9	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPP_F_9) Same description as bit 0.
8	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPP_F_8) Same description as bit 0.
7	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPP_F_7) Same description as bit 0.
6	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPP_F_6) Same description as bit 0.
5	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPP_F_5) Same description as bit 0.
4	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPP_F_4) Same description as bit 0.
3	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPP_F_3) Same description as bit 0.
2	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPP_F_2) Same description as bit 0.
1	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPP_F_1) Same description as bit 0.
0	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPP_F_0) This bit is used to enable/disable the generation of APIC interrupt when the corresponding GPI_INT_STS bit is set. 0 = disable interrupt generation 1 = enable interrupt generation Refer to GPI_IRQ_ROUTE for host GPIO Driver Mode interrupt routing.