GPI Interrupt Enable (GPI_IE_GPP_J_0) – Offset 228 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Introduction
CNVi WiFi* PCI Configuration
eSPI PCI Configuration
eSPI PCR
GPIO Commumity 0
GPIO Commumity 1
GPIO Commumity 2
GPIO Commumity 3
GPIO Commumity 4
GPIO Commumity 5
GSPI Additional MMIO
GSPI DMA
GSPI MMIO
GSPI PCI Configuration
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Integrated Sensor Hub (ISH) PCI Configuration
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Intel(R) Management Engine Interface (MEI) PCI Configuration
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PMC PCI Configuration
PMC SSRAM PCI Configuration
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- AHCI Index Register (INDEX)
- AHCI Data Register (DATA)
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SATA MXPBA
- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
- MSI-X Pending Bit Array QW 1 (MXPQW0_DW1)
SATA MXTBA
SATA PCI Configuration
SATA Port 0 ABAR
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SATA Port 2 ABAR
SATA Port 3 ABAR
SATA Port 4 ABAR
SATA Port 5 ABAR
SATA Port 6 ABAR
SATA Port 7 ABAR
SMBus MMIO and I/O
SMBus PCI Configuration
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SPI PCI Configuration
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- Device Idle Control Register (THC_M_CMN_DEVIDLECTRL)
- THC LTR Control Register (THC_M_CMN_LTR_CTRL)
THC MMIO Port
THC PCI Configuration
UART Additional MMIO
UART DMA
UART MMIO
UART PCI Configuration
USB MMIO
USB PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration

GPI Interrupt Enable (GPI_IE_GPP_J_0) – Offset 228

Bit Range	Default	Access	Field Name and Description
31:17	0h	RO	Reserved
16	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPP_J_16) Same description as bit 0.
15	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPP_J_15) Same description as bit 0.
14	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPP_J_14) Same description as bit 0.
13	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPP_J_13) Same description as bit 0.
12	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPP_J_12) Same description as bit 0.
11	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPP_J_11) Same description as bit 0.
10	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPP_J_10) Same description as bit 0.
9	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPP_J_9) Same description as bit 0.
8	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPP_J_8) Same description as bit 0.
7	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPP_J_7) Same description as bit 0.
6	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPP_J_6) Same description as bit 0.
5	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPP_J_5) Same description as bit 0.
4	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPP_J_4) Same description as bit 0.
3	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPP_J_3) Same description as bit 0.
2	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPP_J_2) Same description as bit 0.
1	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPP_J_1) Same description as bit 0.
0	0h	RW	GPI Interrupt Enable (GPI_INT_EN_GPP_J_0) This bit is used to enable/disable the generation of APIC interrupt when the corresponding GPI_INT_STS bit is set. 0 = disable interrupt generation 1 = enable interrupt generation Refer to GPI_IRQ_ROUTE for host GPIO Driver Mode interrupt routing.

GPI General Purpose Events Status (GPI_GPE_STS_GPP_D_0)

GPI Interrupt Enable (GPI_IE_GPP_R_0) GPI General Purpose Events Status (GPI_GPE_STS_GPP_D_0)