GPI Interrupt Status (GPI_IS_DSW_0) – Offset 200 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

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xDCI PCI Configuration

GPI Interrupt Status (GPI_IS_DSW_0) – Offset 200

Refer to Register Field for detail

Bit Range	Default	Access	Field Name and Description
31:17	0h	RO	Reserved (RSVD_0) Reserved
16:13	0h	RO	Reserved
12	0h	RW/1C/V	GPI Interrupt Status (GPI_INT_STS_GPD_12) Same description as bit 0.
11	0h	RW/1C/V	GPI Interrupt Status (GPI_INT_STS_GPD_11) Same description as bit 0.
10	0h	RW/1C/V	GPI Interrupt Status (GPI_INT_STS_GPD_10) Same description as bit 0.
9	0h	RW/1C/V	GPI Interrupt Status (GPI_INT_STS_GPD_9) Same description as bit 0.
8	0h	RW/1C/V	GPI Interrupt Status (GPI_INT_STS_GPD_8) Same description as bit 0.
7	0h	RW/1C/V	GPI Interrupt Status (GPI_INT_STS_GPD_7) Same description as bit 0.
6	0h	RW/1C/V	GPI Interrupt Status (GPI_INT_STS_GPD_6) Same description as bit 0.
5	0h	RW/1C/V	GPI Interrupt Status (GPI_INT_STS_GPD_5) Same description as bit 0.
4	0h	RW/1C/V	GPI Interrupt Status (GPI_INT_STS_GPD_4) Same description as bit 0.
3	0h	RW/1C/V	GPI Interrupt Status (GPI_INT_STS_GPD_3) Same description as bit 0.
2	0h	RW/1C/V	GPI Interrupt Status (GPI_INT_STS_GPD_2) Same description as bit 0.
1	0h	RW/1C/V	GPI Interrupt Status (GPI_INT_STS_GPD_1) Same description as bit 0.
0	0h	RW/1C/V	GPI Interrupt Status (GPI_INT_STS_GPD_0) This bit is set to '1' by hardware when either an edge or a level event is detected (See RxEdCfg RxInv) on pad and all the following conditions are true: - The corresponding pad is used in GPIO input mode - The corresponding PAD_OWN[2:0] is '001' (i.e. Host GPIO Driver Mode). Writing a value of '1' will clear the bit while writing a value of '0' has no effect. 0 = No interrupt 1 = Interrupt asserts The state of GPI_INT_EN does not prevent the setting of GPI_INT_STS.

GPI Interrupt Enable (GPI_IE_DSW_0)

Host Software Pad Ownership (HOSTSW_OWN_DSW_0) GPI Interrupt Enable (GPI_IE_DSW_0)