GPI Interrupt Status (GPI_IS_GPP_C_0) – Offset 204 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

GPI Interrupt Status (GPI_IS_GPP_C_0) – Offset 204

Refer to Register Field for detail

Bit Range	Default	Access	Field Name and Description
31:24	0h	RO	Reserved (RSVD_0) Reserved
23	0h	RW/1C/V	GPI Interrupt Status (GPI_INT_STS_GPP_C_23) Same description as bit 0.
22	0h	RW/1C/V	GPI Interrupt Status (GPI_INT_STS_GPP_C_22) Same description as bit 0.
21	0h	RW/1C/V	GPI Interrupt Status (GPI_INT_STS_GPP_C_21) Same description as bit 0.
20	0h	RW/1C/V	GPI Interrupt Status (GPI_INT_STS_GPP_C_20) Same description as bit 0.
19	0h	RW/1C/V	GPI Interrupt Status (GPI_INT_STS_GPP_C_19) Same description as bit 0.
18	0h	RW/1C/V	GPI Interrupt Status (GPI_INT_STS_GPP_C_18) Same description as bit 0.
17	0h	RW/1C/V	GPI Interrupt Status (GPI_INT_STS_GPP_C_17) Same description as bit 0.
16	0h	RW/1C/V	GPI Interrupt Status (GPI_INT_STS_GPP_C_16) Same description as bit 0.
15	0h	RW/1C/V	GPI Interrupt Status (GPI_INT_STS_GPP_C_15) Same description as bit 0.
14	0h	RW/1C/V	GPI Interrupt Status (GPI_INT_STS_GPP_C_14) Same description as bit 0.
13	0h	RW/1C/V	GPI Interrupt Status (GPI_INT_STS_GPP_C_13) Same description as bit 0.
12	0h	RW/1C/V	GPI Interrupt Status (GPI_INT_STS_GPP_C_12) Same description as bit 0.
11	0h	RW/1C/V	GPI Interrupt Status (GPI_INT_STS_GPP_C_11) Same description as bit 0.
10	0h	RW/1C/V	GPI Interrupt Status (GPI_INT_STS_GPP_C_10) Same description as bit 0.
9	0h	RW/1C/V	GPI Interrupt Status (GPI_INT_STS_GPP_C_9) Same description as bit 0.
8	0h	RW/1C/V	GPI Interrupt Status (GPI_INT_STS_GPP_C_8) Same description as bit 0.
7	0h	RW/1C/V	GPI Interrupt Status (GPI_INT_STS_GPP_C_7) Same description as bit 0.
6	0h	RW/1C/V	GPI Interrupt Status (GPI_INT_STS_GPP_C_6) Same description as bit 0.
5	0h	RW/1C/V	GPI Interrupt Status (GPI_INT_STS_GPP_C_5) Same description as bit 0.
4	0h	RW/1C/V	GPI Interrupt Status (GPI_INT_STS_GPP_C_4) Same description as bit 0.
3	0h	RW/1C/V	GPI Interrupt Status (GPI_INT_STS_GPP_C_3) Same description as bit 0.
2	0h	RW/1C/V	GPI Interrupt Status (GPI_INT_STS_GPP_C_2) Same description as bit 0.
1	0h	RW/1C/V	GPI Interrupt Status (GPI_INT_STS_GPP_C_1) Same description as bit 0.
0	0h	RW/1C/V	GPI Interrupt Status (GPI_INT_STS_GPP_C_0) This bit is set to '1' by hardware when either an edge or a level event is detected (See RxEdCfg RxInv) on pad and all the following conditions are true: - The corresponding pad is used in GPIO input mode - The corresponding PAD_OWN[2:0] is '001' (i.e. Host GPIO Driver Mode). Writing a value of '1' will clear the bit while writing a value of '0' has no effect. 0 = No interrupt 1 = Interrupt asserts The state of GPI_INT_EN does not prevent the setting of GPI_INT_STS.