GPIO Serial Blink Enable (GP_SER_BLINK) – Offset 344 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

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GPIO Serial Blink Enable (GP_SER_BLINK) – Offset 344

Bit Range	Default	Access	Field Name and Description
31:5	0h	RO	Reserved (RSVD_0) Reserved
4:0	0h	RW	GP SER BLINK (GP_SER_BLINK) The setting of this bit has no effect if the corresponding GPIO is programmed as an input, if the corresponding GPIO has the PWM enabled, or if Serial Blink capability does not exist . This bit should be set to a 1 before output buffer is enabled. When set to a '0', the corresponding GPIO will function normally. This bit should be set to a 1 while the corresponding PMode bit is set to 0h (GPIO Mode). Setting the PMode bit to other value (non-GPIO Mode) after the GP_SER_BLINK bit ensures PCH will not drive a 1 on the pin as an output. When this corresponding bit is set to a 1 and the pin is configured to output mode, the serial blink capability is enabled and the programmed message is serialized out through an open-drain buffer configuration. The value of the corresponding GPIOTxState bit remains unchanged and does not impact the serial blink capability in any way. Writes to this register have no effect when the corresponding pin is configured in native mode and the read value returned is undefined. Bit0 = pad 0 Bit1 = pad 1 Bit2 = pad 2 ... Bit N-1= Pad N-1 Note: N is the number of Pads in the Community.

Bit Range

Default

Access

Field Name and Description

31:5

Reserved (RSVD_0)

Reserved

4:0

GP SER BLINK (GP_SER_BLINK)

The setting of this bit has no effect if the corresponding GPIO is programmed as an input, if the corresponding GPIO has the PWM enabled, or if Serial Blink capability does not exist . This bit should be set to a 1 before output buffer is enabled.
When set to a '0', the corresponding GPIO will function normally.
This bit should be set to a 1 while the corresponding PMode bit is set to 0h (GPIO Mode). Setting the PMode bit to other value (non-GPIO Mode) after the GP_SER_BLINK bit ensures PCH will not drive a 1 on the pin as an output.
When this corresponding bit is set to a 1 and the pin is configured to output mode, the serial blink capability is enabled and the programmed message is serialized out through an open-drain buffer configuration.
The value of the corresponding GPIOTxState bit remains unchanged and does not impact the serial blink capability in any way.
Writes to this register have no effect when the corresponding pin is configured in native mode and the read value returned is undefined.
Bit0 = pad 0
Bit1 = pad 1
Bit2 = pad 2
...
Bit N-1= Pad N-1
Note: N is the number of Pads in the Community.

GPIO Serial Blink Command/Status (GP_SER_CMDSTS)

PWM Control (PWMC) GPIO Serial Blink Command/Status (GP_SER_CMDSTS)

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Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

GPIO Serial Blink Enable (GP_SER_BLINK) – Offset 344