GSX Channel-0 Capabilities DW0 (GSX_C0CAP_DW0) – Offset 358 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Introduction
CNVi WiFi* PCI Configuration
eSPI PCI Configuration
eSPI PCR
GPIO Commumity 0
GPIO Commumity 1
GPIO Commumity 2
GPIO Commumity 3
GPIO Commumity 4
GPIO Commumity 5
GSPI Additional MMIO
GSPI DMA
GSPI MMIO
GSPI PCI Configuration
I2C Additional MMIO
I2C DMA
I2C MMIO
I3C / I2C / UART / GSPI PCR
I3C Additional MMIO
I3C DMA
I3C MMIO
I3C PCI Configuration
IDE-Redirect (IDE-R) PCI Configuration
Integrated GbE PCI Configuration
Integrated Sensor Hub (ISH) MMIO
Integrated Sensor Hub (ISH) PCI Configuration
Intel(R) Management Engine Interface (MEI) MMIO
Intel(R) Management Engine Interface (MEI) PCI Configuration
Intel® High Definition Audio MMIO
Intel® High Definition Audio PCI Configuration
Intergrated GbE MMIO
Keyboard and Text (KT) PCI Configuration
P2SB PCI Configuration
PCIe* PCI Configuration
PMC I/O Based
PMC MMIO
PMC PCI Configuration
PMC SSRAM PCI Configuration
RTC Index
RTC PCR
SATA ABAR
SATA AIDPBA
- AHCI Index Register (INDEX)
- AHCI Data Register (DATA)
SATA Initialization (SIR) Index
SATA MXPBA
- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
- MSI-X Pending Bit Array QW 1 (MXPQW0_DW1)
SATA MXTBA
SATA PCI Configuration
SATA Port 0 ABAR
SATA Port 1 ABAR
SATA Port 2 ABAR
SATA Port 3 ABAR
SATA Port 4 ABAR
SATA Port 5 ABAR
SATA Port 6 ABAR
SATA Port 7 ABAR
SMBus MMIO and I/O
SMBus PCI Configuration
SMBus PCR
SMBus TCO I/O
SPI MMIO
SPI PCI Configuration
THC MMIO Common
- Device Idle Control Register (THC_M_CMN_DEVIDLECTRL)
- THC LTR Control Register (THC_M_CMN_LTR_CTRL)
THC MMIO Port
THC PCI Configuration
UART Additional MMIO
UART DMA
UART MMIO
UART PCI Configuration
USB MMIO
USB PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration

GSX Channel-0 Capabilities DW0 (GSX_C0CAP_DW0) – Offset 358

Bit Range	Default	Access	Field Name and Description
31:12	0h	RO	Reserved (RSVD_0) Reserved
11:10	0h	RO	Power Well (PW) Indicates the power well. 00: means Core power well 01: reserved 1x: reserved
9:5	0h	RW/O	Number of Output Expanders (NOUT) BIOS programs this field to indicate number of output expander components which corresponds to multiple of CxGPO in byte granularity. This field is 1-based ('00001' means 1 output expander which produces 8 bits of CxGPO). If this channel does not have output, this register shall be written with value of '00000'.
4:0	0h	RW/O	Number of Input Expanders (NIN) BIOS programs this field to indicate number of input expander components which corresponds to multiple of CxGPO. This field is 1-based ('00001' means 1 input expander which produces 8 bits of CxGPI). If this channel does not have input, this register shall be written with value of '00000'. Typically, the combine total value of supported NOUT+NIN <= 8.

GSX Channel-0 Capabilities DW1 (GSX_C0CAP_DW1)

GSX Controller Capabilities (GSX_CAP) GSX Channel-0 Capabilities DW1 (GSX_C0CAP_DW1)

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Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

GSX Channel-0 Capabilities DW0 (GSX_C0CAP_DW0) – Offset 358