GSX Channel-0 Command (GSX_C0CMD) – Offset 370 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

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Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

GSX Channel-0 Command (GSX_C0CMD) – Offset 370

Bit Range	Default	Access	Field Name and Description
31:4	0h	RO	Reserved (RSVD_0) Reserved
3	0h	RW/1S/V	Input and Output Expander Reset Sequence (IOERST) Software writes '1' to this bit to cause a reset sequence that brings both input and output expander into a default state. Serialization process will be able to begin at default bit position again. Specifically: GSXSRESET# going to output expanders is asserted while GSXSLOAD shall be held in '0' logic state such that any stale pin state previously latched into input expanders is being reloaded. The serialization thereafter can start from default bit position. Hardware automatically clears the bit to zero after the process above has been completed. Software shall have both ST and RUN bit equal to '0' when setting IOERST to '1'.
2	0h	RO/V	Running (RUN) This bit reflects the status of the serialization process. A '1' indicates that the serialization process is in progress. When software clears the ST bit, software shall poll on RUN bit to be '0' before software can write '1' to ST bit again.
1	0h	RO/V	Busy (BSY) Software reads this field to determine if the serialization of most recently updated GPOLVL_DW1 and/or GPOLVL_DW0 content has been completely serialized out on the GSX. H/w sets this bit when either GPOLVL_DW1 or GPOLVL_DW0 is written to. Hardware will automatically clear the bit to'0' after all of the newly written value of GPOLVL_DW1 and/or GPOLVL_DW0 bits have been serialized out at least once. This allows software a method to ensure no collapsing of any particular CxGPO[y] bit during a back to back software update of GPOLVL_DW0 or GPOLVL_DW1. Software may reprogram the GPOLVL_DW1 and/or GPOLVL_DW0 at any time irrespective of state of BSY bit if intermediate software update being collapsed is not a concern. Irrespective of the state of BSY bit, hardware serialization process walks thru each bit of GPOLVL_DW1 & GPOLVL_DW0 from bit[63] to bit[0] in descending order. Example: if hardware serialization is in the midst of serializing out CxGPO[3] and software updates GPOLVL_DW0, hardware serialization will serialize out the updated value of GPOLVL_DW0[2 to 0] as CxGPO[2:0]. Then hardware will serialize out the updated value of GPOLVL_DW1[MSB to 0] and so on (assuming >4 output expanders case). \t\t\t
0	0h	RW	Start (ST) This bit is set to 1 by software to start the serialization process. Software should not write this bit to 1 unless: - The Busy status bit is cleared, and - The CxCAP has been programmed. Once this bit is set to 1, the serialization processes for input and output are running continuously. If software clears the ST bit to '0', hardware shall stop the serialization process at a convenient time but at atomic boundary. Note: Clearing Start bit does not trigger GSXSRESET# to be asserted.