HBA Capabilities (GHC_CAP) – Offset 0 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

HBA Capabilities (GHC_CAP) – Offset 0

This register indicates basic capabilities of the HBA to driver software. The RWO bits in this register are only cleared upon PLTRST#. This register is not reset by FLR.

Bit Range	Default	Access	Field Name and Description
31	1h	RW/O	Supports 64-bit Addressing (S64A) Indicates the S-ATA controller can access 64-bit data structures. The 32-bit upper bits of the port DMA Descriptor, the PRD Base, and each PRD entry are read/write.
30	1h	RW/O	Supports Native Command Queuing Acceleration (SCQA) Indicates the SATA controller supports Serial-ATA Native Command Queueing. The HBA will handle DMA Setup FISes in hardware, including support for auto-activiate optimization through the FIS.
29	1h	RW/O	Supports SNotification Register (SSNTF) When set to 1, indicates that the HBA supports the PxSNTF (SNotification) register and its associated functionality. When cleared to 0, the HBA does not support the PxSNTF (SNotification) register and its associated functionality.
28	1h	RW/O	Supports Mechanical Presence Switch (SMPS) When set to 1, the HBA supports mechanical presence switches on its ports for use in hot plug operations. When cleared to 0, this function is not supported. This value is loaded by the BIOS prior to OS initialization.
27	1h	RW/O	Supports Staggered Spin-up (SSS) Indicates whether the SATA controller supports staggered spin-up on its ports, for use in balancing power spikes. This value is loaded by platform BIOS prior to OS initiallization.
26	1h	RW/O	Supports Aggressive Link Power Management (SALP) Indicates the SATA controller supports auto-generating link requests to the partial or slumber states when there are no commands to process. When cleared to 0, software shall treat the PxCMD.ALPE and PxCMD.ASP bits as reserved.
25	1h	RW/O	Supports Activity LED (SAL) Indicates the SATA controller supports a single output pin (SATALED#) which indicates activity.
24	1h	RW/O	Supports Command List Override (SCLO) When set to 1, indicates that the HBA supports the PxCMD.CLO bit and it's associated function. When cleared to 0, The HBA is not capable of clearing the BSY and DRQ bits in the Status register in order to issue a software reset if these bits are still set from a previous operation.
23:20	3h	RW/O	Interface Speed Support (ISS) Indicates the maximum speed the SATA controller can support on its ports. These encodings match the system software programmable PxSCTL.DET.SPD field. 0000 = Reserved; 0001 = Gen 1 (1.5 Gbps); 0010 = Gen 2 (3 Gbps); 0011 = Gen 3 (6 Gbps); 0100 - 1111 = Reserved. If (FFSATA0p0, FFSATA0p1, FFSATA0p2, FFSATA0p3, FFSATA0p4 ,FFSATA0p5, FFSATA0p6 and FFSATA0p7) are all 1, this field is RWO defaulting to 0010 and ignores software write value of 0011. If either FFSATA0p0, FFSATA0p1, FFSATA0p2, FFSATA0p3, FFSATA0p4 , FFSATA0p5, FFSATA0p6 or FFSATA0p7 is 0, this field is RWO defaulting to 0011.
19	0h	RO	RSVD0 (RSVD0) Reserved
18	1h	RO	Supports AHCI mode only (SAM) The SATA controller may optionally support AHCI access mechanism only. A value of 0 indicates that in addition to the native AHCI mechanism (via ABAR), the SATA controller implements a legacy, task-file based register interface such as SFF-8038i. A value of 1 indicates that the SATA controller does not implement a legacy, task-file based register interface.
17	1h	RW/O	Supports Port Multiplier (SPM) The SATA controller may optionally support command-based switching Port Multipliers. BIOS must clear this bit if Port Multipliers are not supported.
16	0h	RO	FIS-based Switching Supported (FBSS) Not supported.
15	1h	RO	PIO Multiple DRQ Block (PMD) If set to 1, the HBA supports multiple DRQ block data transfers for the PIO command protocol.
14	1h	RW/O	Slumber State Capable (SSC) The SATA controller supports the slumber state.
13	1h	RW/O	Partial State Capable (PSC) The SATA controller supports the partial state.
12:8	1fh	RO	Number of Command Slots (NCS) 1Fh indicating support for 32 slots.
7	0h	RO	Command Completion Coalescing Supported (CCCS) When set to 1, indicates that the HBA supports command completion coalescing. When command completion coalescing is supported, the HBA has implemented the CCC_CTL and the CCC_PORTS global HBA registers. When cleared to 0, indicates that the HBA does not support command completion coalescing and the CCC_CTL and CCC_PORTS global HBA registers are not implemented.
6	0h	RW/O/V	Enclosure Management Supported (EMS) When set to 1, indicates that the HBA supports enclosure management. When enclosure management is supported, the HBA has implemented the EM_LOC and EM_CTL global HBA registers. When cleared to 0, indicates that the HBA does not support enclosure management and the EM_LOC and EM_CTL global HBA registers are not implemented.
5	0h	RW/O	Supports External SATA (SXS) When set to 1, indicates that the HBA has one or more Serial ATA ports that has a signal only connector that is externally accessible. If this bit is set, software may refer to the PxCMD.ESP bit to determine whether a specific port has its signal connector externally accessible as a signal only connector (i.e. power is not part of that connector). When the bit is cleared to 0, indicates that the HBA has no Serial ATA ports that have a signal only connector externally accessible.
4:0	7h	RO/V	Number of Ports (NP) 0's based value indicating the maximum number of ports supported. Note that the number of ports indicated in this field may be more than the number of ports indicated in the PI register.