HECI Command (HECI1_CMD) – Offset 4 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Introduction
CNVi WiFi* PCI Configuration
eSPI PCI Configuration
eSPI PCR
GPIO Commumity 0
GPIO Commumity 1
GPIO Commumity 2
GPIO Commumity 3
GPIO Commumity 4
GPIO Commumity 5
GSPI Additional MMIO
GSPI DMA
GSPI MMIO
GSPI PCI Configuration
I2C Additional MMIO
I2C DMA
I2C MMIO
I3C / I2C / UART / GSPI PCR
I3C Additional MMIO
I3C DMA
I3C MMIO
I3C PCI Configuration
IDE-Redirect (IDE-R) PCI Configuration
Integrated GbE PCI Configuration
Integrated Sensor Hub (ISH) MMIO
Integrated Sensor Hub (ISH) PCI Configuration
Intel(R) Management Engine Interface (MEI) MMIO
Intel(R) Management Engine Interface (MEI) PCI Configuration
Intel® High Definition Audio MMIO
Intel® High Definition Audio PCI Configuration
Intergrated GbE MMIO
Keyboard and Text (KT) PCI Configuration
P2SB PCI Configuration
PCIe* PCI Configuration
PMC I/O Based
PMC MMIO
PMC PCI Configuration
PMC SSRAM PCI Configuration
RTC Index
RTC PCR
SATA ABAR
SATA AIDPBA
- AHCI Index Register (INDEX)
- AHCI Data Register (DATA)
SATA Initialization (SIR) Index
SATA MXPBA
- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
- MSI-X Pending Bit Array QW 1 (MXPQW0_DW1)
SATA MXTBA
SATA PCI Configuration
SATA Port 0 ABAR
SATA Port 1 ABAR
SATA Port 2 ABAR
SATA Port 3 ABAR
SATA Port 4 ABAR
SATA Port 5 ABAR
SATA Port 6 ABAR
SATA Port 7 ABAR
SMBus MMIO and I/O
SMBus PCI Configuration
SMBus PCR
SMBus TCO I/O
SPI MMIO
SPI PCI Configuration
THC MMIO Common
- Device Idle Control Register (THC_M_CMN_DEVIDLECTRL)
- THC LTR Control Register (THC_M_CMN_LTR_CTRL)
THC MMIO Port
THC PCI Configuration
UART Additional MMIO
UART DMA
UART MMIO
UART PCI Configuration
USB MMIO
USB PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration

HECI Command (HECI1_CMD) – Offset 4

HECI Command Register

Bit Range	Default	Access	Field Name and Description
15:11	0h	RO	Reserved (RSVD) Reserved.
10	0h	RW	Interrupt Disable (ID) Disables this device from generating PCI line based interrupts. This bit does not have any effect on MSI operation.
9	0h	RO	Fast Back-to-Back Enable (FBE) Not implemented, hardwired to 0.
8	0h	RO	SERR# Enable (SEE) Not implemented, hardwired to 0.
7	0h	RO	Wait Cycle Enable (WCC) Not implemented, hardwired to 0.
6	0h	RO	Parity Error Response Enable (PEE) Not implemented, hardwired to 0.
5	0h	RO	VGA Palette Snooping Enable (VAG) Not implemented, hardwired to 0
4	0h	RO	Memory Write And Invalidate Enable (MWIE) Not implemented, hardwired to 0.
3	0h	RO	Special Cycle Enable (SCE) Not implemented, hardwired to 0.
2	0h	RW	Bus Master Enable (BME) Controls the HECI host controller's abiity to act as a system memory master for data transfers. When this bit is cleared, HECI bus master activity stops and any active DMA engines return to an idle condition. This bit is made visible to firmware through the H_PCI_CSR register, and changes to this bit may be configured by the H_PCI_CSR register to generate an MSI to mIA. When this bit is '0', HECI is blocked from generating MSI to the host CPU. Note that this bit does not block HECI accesses to CSE-UMA.
1	0h	RW	Memory Space Enable (MSE) Controls access to the HECI host controller's memory mapped register space.
0	0h	RO	I/O Space Enable (IOSE) Not implemented, hardwired to 0.

HECI Status (HECI1_STS)

HECI ID (HECI1_ID) HECI Status (HECI1_STS)