Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2
ID | Date | Version | Classification |
---|---|---|---|
834576 | 10/10/2024 | 001 | Public |
High Speed Configuration 2 (HSCFG2) – Offset a4
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:19 | 0h | RO | Rsvd1 (RSVD1) Rsvd1 |
18 | 0h | RW | PORT1 Host Mode Override (PORT1_HOST_MODE_OVERRIDE) When set, this bit causes the Host_Device mux on port 1 to be forced into the Host mode. |
17:16 | 0h | RW | eUSB2SEL (EUSB2SEL) The two bits are associate with USB2 ports 1 - bit 16 and 2 - bit 2 |
15 | 0h | RW | HS ASYNC Active IN Mask (HSAAIM) Determines if the Async Active will mask/ignore IN EP s. |
14 | 0h | RW | HS OUT ASYNC Active Polling EP Mask (HSOAAPEPM) Determines if the Async Active for OUT HS/FS/LS masks/ignores EP s that are polling/PINGing (HS) due to NAK. |
13 | 0h | RW | HS IN ASYNC Active Polling EP Mask (HSIAAPEPM) Determines if the Async Active for IN HS/FS/LS masks/ignores EP s that are polling due to NAK. |
12:11 | 3h | RW | HS INTR IN Periodic Active Policy Control (HSIIPAPC) Controls how the HS INTR IN periodic active is used to generate the global periodic active. This will determine how the smallest service interval among active EP s and number of active EP s are used. |
10:4 | 0h | RW | HS INTR IN Periodic Active Num of EP Threshold (HSIIPANEPT) Defines the threshold used to determine if Periodic Acive may include HS/FS/LS INTR IN EP active indication. If there are more than NumEPThreshold active HS/FS/LS INTR EP s then they may be included as part of the periodic active generation. |
3:0 | 0h | RW | HS INTR IN Periodic Active Service Interval Threshold (HSIIPASIT) Defines the Service Interval threshold used to determine if Periodic Acive will include HS/FS/LS INTR IN EP active indication. If there are any active HS/FS/LS INTR EP s with a service interval less than or equal to this threshold then they may be included as part of the periodic active generation. |