Host Configuration (HCFG) – Offset 40 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Introduction
CNVi WiFi* PCI Configuration
eSPI PCI Configuration
eSPI PCR
GPIO Commumity 0
GPIO Commumity 1
GPIO Commumity 2
GPIO Commumity 3
GPIO Commumity 4
GPIO Commumity 5
GSPI Additional MMIO
GSPI DMA
GSPI MMIO
GSPI PCI Configuration
I2C Additional MMIO
I2C DMA
I2C MMIO
I3C / I2C / UART / GSPI PCR
I3C Additional MMIO
I3C DMA
I3C MMIO
I3C PCI Configuration
IDE-Redirect (IDE-R) PCI Configuration
Integrated GbE PCI Configuration
Integrated Sensor Hub (ISH) MMIO
Integrated Sensor Hub (ISH) PCI Configuration
Intel(R) Management Engine Interface (MEI) MMIO
Intel(R) Management Engine Interface (MEI) PCI Configuration
Intel® High Definition Audio MMIO
Intel® High Definition Audio PCI Configuration
Intergrated GbE MMIO
Keyboard and Text (KT) PCI Configuration
P2SB PCI Configuration
PCIe* PCI Configuration
PMC I/O Based
PMC MMIO
PMC PCI Configuration
PMC SSRAM PCI Configuration
RTC Index
RTC PCR
SATA ABAR
SATA AIDPBA
- AHCI Index Register (INDEX)
- AHCI Data Register (DATA)
SATA Initialization (SIR) Index
SATA MXPBA
- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
- MSI-X Pending Bit Array QW 1 (MXPQW0_DW1)
SATA MXTBA
SATA PCI Configuration
SATA Port 0 ABAR
SATA Port 1 ABAR
SATA Port 2 ABAR
SATA Port 3 ABAR
SATA Port 4 ABAR
SATA Port 5 ABAR
SATA Port 6 ABAR
SATA Port 7 ABAR
SMBus MMIO and I/O
SMBus PCI Configuration
SMBus PCR
SMBus TCO I/O
SPI MMIO
SPI PCI Configuration
THC MMIO Common
- Device Idle Control Register (THC_M_CMN_DEVIDLECTRL)
- THC LTR Control Register (THC_M_CMN_LTR_CTRL)
THC MMIO Port
THC PCI Configuration
UART Additional MMIO
UART DMA
UART MMIO
UART PCI Configuration
USB MMIO
USB PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration

Host Configuration (HCFG) – Offset 40

Host Configuration

Bit Range	Default	Access	Field Name and Description
7:5	0h	RO	Reserved (RSVD) Reserved
4	0h	RW/1L	SPD Write Disable (SPDWD) This bit is must be set to '1' to disable writes to SPD which are on Host SMB address ranges A0h - AEh. The SMBus range is unwriteable until next platform reset. HW Default is '0.' Note: This bit is RW O and will be reset on PLTRST# reset. This should be set by BIOS memory reference code to '1'. SW can only program this bit when both HCTL(6) = 0 (START) and HSTS(0) = 0 (HBSY), else it may result in an undefined behavior. [Noted in HSTS.HBSY that states "No SMB registers should be accessed while HSTS.HBSY bit is set, the same will apply to SPD write disable. 3 RW 0 SSRESET : Soft SMBUS Reset: When this bit is 1,
3	0h	RW	SSRESET (SSRESET) Soft SMBUS Reset: When this bit is 1, the SMbus state machine and logic in PCH is reset. The HW will reset this bit to 0 when reset operation is completed.
2	0h	RW	I2C_EN (I2CEN) When this bit is 1, the Intel PCH is enabled to communicate with I2C devices. This will change the formatting of some commands. When this bit is 0, behavior is for SMBus.
1	0h	RW	SMB_SMI_EN (SSEN) When this bit is set, any source of an SMB interrupt will instead be routed to generate an SMI#. Refer to Section 6.7 (Interrupts/SMI#) for details.
0	0h	RW	HST_EN (HSTEN) When set, the SMB Host Controller interface is enabled to execute commands. The HST_INT_EN bit needs to be enabled in order for the SMB Host Controller to interrupt or SMI#. Additionally, the SMB Host Controller will not respond to any new requests until all interrupt requests have been cleared.

TCO Base Address (TCOBASE)

Interrupt Pin (INTPN) TCO Base Address (TCOBASE)

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Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Host Configuration (HCFG) – Offset 40