Host Software Pad Ownership (HOSTSW_OWN_DSW_0) – Offset 150 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Introduction
CNVi WiFi* PCI Configuration
eSPI PCI Configuration
eSPI PCR
GPIO Commumity 0
GPIO Commumity 1
GPIO Commumity 2
GPIO Commumity 3
GPIO Commumity 4
GPIO Commumity 5
GSPI Additional MMIO
GSPI DMA
GSPI MMIO
GSPI PCI Configuration
I2C Additional MMIO
I2C DMA
I2C MMIO
I3C / I2C / UART / GSPI PCR
I3C Additional MMIO
I3C DMA
I3C MMIO
I3C PCI Configuration
IDE-Redirect (IDE-R) PCI Configuration
Integrated GbE PCI Configuration
Integrated Sensor Hub (ISH) MMIO
Integrated Sensor Hub (ISH) PCI Configuration
Intel(R) Management Engine Interface (MEI) MMIO
Intel(R) Management Engine Interface (MEI) PCI Configuration
Intel® High Definition Audio MMIO
Intel® High Definition Audio PCI Configuration
Intergrated GbE MMIO
Keyboard and Text (KT) PCI Configuration
P2SB PCI Configuration
PCIe* PCI Configuration
PMC I/O Based
PMC MMIO
PMC PCI Configuration
PMC SSRAM PCI Configuration
RTC Index
RTC PCR
SATA ABAR
SATA AIDPBA
- AHCI Index Register (INDEX)
- AHCI Data Register (DATA)
SATA Initialization (SIR) Index
SATA MXPBA
- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
- MSI-X Pending Bit Array QW 1 (MXPQW0_DW1)
SATA MXTBA
SATA PCI Configuration
SATA Port 0 ABAR
SATA Port 1 ABAR
SATA Port 2 ABAR
SATA Port 3 ABAR
SATA Port 4 ABAR
SATA Port 5 ABAR
SATA Port 6 ABAR
SATA Port 7 ABAR
SMBus MMIO and I/O
SMBus PCI Configuration
SMBus PCR
SMBus TCO I/O
SPI MMIO
SPI PCI Configuration
THC MMIO Common
- Device Idle Control Register (THC_M_CMN_DEVIDLECTRL)
- THC LTR Control Register (THC_M_CMN_LTR_CTRL)
THC MMIO Port
THC PCI Configuration
UART Additional MMIO
UART DMA
UART MMIO
UART PCI Configuration
USB MMIO
USB PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration

Host Software Pad Ownership (HOSTSW_OWN_DSW_0) – Offset 150

Refer to Register Field for detail

Bit Range	Default	Access	Field Name and Description
31:17	0h	RO	Reserved (RSVD_0) Reserved
16:13	0h	RO	Reserved
12	0h	RW	HostSW_Own (HOSTSW_OWN_GPD_12) Same description as bit 0.
11	0h	RW	HostSW_Own (HOSTSW_OWN_GPD_11) Same description as bit 0.
10	0h	RW	HostSW_Own (HOSTSW_OWN_GPD_10) Same description as bit 0.
9	0h	RW	HostSW_Own (HOSTSW_OWN_GPD_9) Same description as bit 0.
8	0h	RW	HostSW_Own (HOSTSW_OWN_GPD_8) Same description as bit 0.
7	0h	RW	HostSW_Own (HOSTSW_OWN_GPD_7) Same description as bit 0.
6	0h	RW	HostSW_Own (HOSTSW_OWN_GPD_6) Same description as bit 0.
5	0h	RW	HostSW_Own (HOSTSW_OWN_GPD_5) Same description as bit 0.
4	0h	RW	HostSW_Own (HOSTSW_OWN_GPD_4) Same description as bit 0.
3	0h	RW	HostSW_Own (HOSTSW_OWN_GPD_3) Same description as bit 0.
2	0h	RW	HostSW_Own (HOSTSW_OWN_GPD_2) Same description as bit 0.
1	0h	RW	HostSW_Own (HOSTSW_OWN_GPD_1) Same description as bit 0.
0	0h	RW	HostSW_Own (HOSTSW_OWN_GPD_0) This register determines the appropriate host status bit update when a pad is under host ownership (refer to PAD_OWN). 0 = ACPI Mode. GPIO input event updates are limited to GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS. GPI_STS update is masked. 1 = GPIO Driver Mode. GPIO input event updates are limited to GPI_STS. GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS updates are masked. Note: Each of the bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. e.g. if the PadCfgLock of pad0 is 1, bit0 is locked down to read-only.

GPI Interrupt Status (GPI_IS_DSW_0)

Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_DSW_0) GPI Interrupt Status (GPI_IS_DSW_0)

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Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Host Software Pad Ownership (HOSTSW_OWN_DSW_0) – Offset 150