Host Software Pad Ownership (HOSTSW_OWN_GPP_I_0) – Offset 150 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

Host Software Pad Ownership (HOSTSW_OWN_GPP_I_0) – Offset 150

Bit Range	Default	Access	Field Name and Description
31:21	0h	RO	Reserved (RSVD_0) Reserved
20	0h	RO	HostSW_Own (HOSTSW_OWN_I3C0_CLK_LOOPBK) Same description as bit 0.
19	0h	RO	Reserved
18	0h	RO	HostSW_Own (HOSTSW_OWN_GSPI1_CLK_LOOPBK) Same description as bit 0.
17	0h	RO	HostSW_Own (HOSTSW_OWN_GSPI0_CLK_LOOPBK) Same description as bit 0.
16	0h	RO	HostSW_Own (HOSTSW_OWN_GPP_I_16) Same description as bit 0.
15	0h	RW	HostSW_Own (HOSTSW_OWN_GPP_I_15) Same description as bit 0.
14	0h	RW	HostSW_Own (HOSTSW_OWN_GPP_I_14) Same description as bit 0.
13	0h	RW	HostSW_Own (HOSTSW_OWN_GPP_I_13) Same description as bit 0.
12	0h	RW	HostSW_Own (HOSTSW_OWN_GPP_I_12) Same description as bit 0.
11	0h	RW	HostSW_Own (HOSTSW_OWN_GPP_I_11) Same description as bit 0.
10	0h	RW	HostSW_Own (HOSTSW_OWN_GPP_I_10) Same description as bit 0.
9	0h	RW	HostSW_Own (HOSTSW_OWN_GPP_I_9) Same description as bit 0.
8	0h	RW	HostSW_Own (HOSTSW_OWN_GPP_I_8) Same description as bit 0.
7	0h	RW	HostSW_Own (HOSTSW_OWN_GPP_I_7) Same description as bit 0.
6	0h	RW	HostSW_Own (HOSTSW_OWN_GPP_I_6) Same description as bit 0.
5	0h	RW	HostSW_Own (HOSTSW_OWN_GPP_I_5) Same description as bit 0.
4	0h	RW	HostSW_Own (HOSTSW_OWN_GPP_I_4) Same description as bit 0.
3	0h	RW	HostSW_Own (HOSTSW_OWN_GPP_I_3) Same description as bit 0.
2	0h	RW	HostSW_Own (HOSTSW_OWN_GPP_I_2) Same description as bit 0.
1	0h	RW	HostSW_Own (HOSTSW_OWN_GPP_I_1) Same description as bit 0.
0	0h	RW	HostSW_Own (HOSTSW_OWN_GPP_I_0) This register determines the appropriate host status bit update when a pad is under host ownership (refer to PAD_OWN). 0 = ACPI Mode. GPIO input event updates are limited to GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS. GPI_STS update is masked. 1 = GPIO Driver Mode. GPIO input event updates are limited to GPI_STS. GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS updates are masked. Note: Each of the bit is lock-able dependent on the associated Pad Configuration register PadCfgLock setting. e.g. if the PadCfgLock of pad0 is 1, bit0 is locked down to read-only.

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Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Host Software Pad Ownership (HOSTSW_OWN_GPP_I_0) – Offset 150