HSIO Power Management Configuration Reg 3 (MODPHY_PM_CFG3) – Offset 10c8 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

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eSPI PCI Configuration
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THC PCI Configuration
UART Additional MMIO
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xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration

HSIO Power Management Configuration Reg 3 (MODPHY_PM_CFG3) – Offset 10c8

Bit Range	Default	Access	Field Name and Description
31	0h	RO	Reserved
30	0h	RW	ModPHY Lane SUS Power Domain Dynamic Gating Enable (MLSPDDGE) When this bit is set to 1, ModPHY Lane SUS Well Dynamic Gating is enabled. ModPHY lane SPD is managed using the variables defined in section 6.1.2.4 (PMC SUS Power Gating Interfaces). When this bit is 0, ModPHY Lane SUS Well Gating can still be done at a more coarse level using MLSXSWPGP and MLS0SWPGP fields.
29:2	0h	RO	Reserved
1	0h	RW	ModPHY Per-Lane SUS Power Domain Dynamic Gating Enable (MPLSPDDGE) When this bit is set to 1, ModPHY Per-Lane SUS Well Dynamic Gating is enabled. When this bit is 0, if modPHY lane SUS power domain dynamic gating is enabled, all lanes are gated/ungated together. This bit has no impact if modPHY lane SUS power domain dynamic gating is disabled.
0	0h	RO	Reserved

HSIO Power Management Configuration Reg 4 (MODPHY_PM_CFG4)

HSIO Power Management Configuration Reg 2 (MODPHY_PM_CFG2) HSIO Power Management Configuration Reg 4 (MODPHY_PM_CFG4)

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Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

HSIO Power Management Configuration Reg 3 (MODPHY_PM_CFG3) – Offset 10c8