HSIO Power Management Configuration Reg 4 (MODPHY_PM_CFG4) – Offset 10cc - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

HSIO Power Management Configuration Reg 4 (MODPHY_PM_CFG4) – Offset 10cc

Bit Range	Default	Access	Field Name and Description
31:0	0h	RW	ASL Over-rides [26:0] (ASLOR) This field provides ASL code to take over SPD power gating control. If ASL code sets a bit corresponding to a controller, it implies that PMC shall ignore any other inputs from that controller and assume that the controller is ready for SPD power gating. 0 in a bit position: Use HW interfaces for the controller to manage SPD gating/wake-up. 1 in a bit position: Ignore HW interfaces for the controller, rely only on MSPDRTReq field thats managed by ASL code. Bit 0: Corresponds to PCIe Controller A, Function 0 Bit 1: Corresponds to PCIe Controller A, Function 1 Bit 2: Corresponds to PCIe Controller A, Function 2 Bit 3: Corresponds to PCIe Controller A, Function 3 Bit 4: Corresponds to PCIe Controller B, Function 0 Bit 5: Corresponds to PCIe Controller B, Function 1 Bit 6: Corresponds to PCIe Controller B, Function 2 Bit 7: Corresponds to PCIe Controller B, Function 3 Bit 8: Corresponds to PCIe Controller C, Function 0 Bit 9: Corresponds to PCIe Controller C, Function 1 Bit 10: Corresponds to PCIe Controller C, Function 2 Bit 11: Corresponds to PCIe Controller C, Function 3 Bit 12: Corresponds to SATA Controller Bit 13: Corresponds to Gbe Controller Bit 14: Corresponds to xHCI Controller Bit 15: Corresponds to xDCI Controller Bit 16: Corresponds to UFS Controller Bit 17: Corresponds to PCIe Controller D, Function 0 Bit 18: Corresponds to PCIe Controller D, Function 1 Bit 19: Corresponds to PCIe Controller D, Function 2 Bit 20: Corresponds to PCIe Controller D, Function 3 Bit 21: Corresponds to PCIe Controller E, Function 0 Bit 22: Corresponds to PCIe Controller E, Function 1 Bit 23: Corresponds to PCIe Controller E, Function 2 Bit 24: Corresponds to PCIe Controller E, Function 3 Bit 25: Corresponds to DMI Controller Bit 26: Corresponds to UFS Controller 2 Bit 27: Corresponds to PCIe Controller F, Function 0 Bit 28: Corresponds to PCIe Controller F, Function 1 Bit 29: Corresponds to PCIe Controller F, Function 2 Bit 30: Corresponds to PCIe Controller F, Function 3 Bit 31: Corresponds to GBETSN Controller This field is going to be used in conjunction with MSPDRTReq and MSPDRTRAck fields above. If ASL code intends to over-ride HW decisions, it will set the corresponding bit for a controller/function to 1 in ASLOR and use MSPDRTReq bits to power-up/power-down SPD.

Bit Range

Default

Access

Field Name and Description

31:0

ASL Over-rides [26:0] (ASLOR)

This field provides ASL code to take over SPD power gating control. If ASL code sets a bit corresponding to a controller, it implies that PMC shall ignore any other inputs from that controller and assume that the controller is ready for SPD power gating.

0 in a bit position: Use HW interfaces for the controller to manage SPD gating/wake-up.

1 in a bit position: Ignore HW interfaces for the controller, rely only on MSPDRTReq field thats managed by ASL code.

Bit 0: Corresponds to PCIe Controller A, Function 0

Bit 1: Corresponds to PCIe Controller A, Function 1

Bit 2: Corresponds to PCIe Controller A, Function 2

Bit 3: Corresponds to PCIe Controller A, Function 3

Bit 4: Corresponds to PCIe Controller B, Function 0

Bit 5: Corresponds to PCIe Controller B, Function 1

Bit 6: Corresponds to PCIe Controller B, Function 2

Bit 7: Corresponds to PCIe Controller B, Function 3

Bit 8: Corresponds to PCIe Controller C, Function 0

Bit 9: Corresponds to PCIe Controller C, Function 1

Bit 10: Corresponds to PCIe Controller C, Function 2

Bit 11: Corresponds to PCIe Controller C, Function 3

Bit 12: Corresponds to SATA Controller

Bit 13: Corresponds to Gbe Controller

Bit 14: Corresponds to xHCI Controller

Bit 15: Corresponds to xDCI Controller

Bit 16: Corresponds to UFS Controller

Bit 17: Corresponds to PCIe Controller D, Function 0

Bit 18: Corresponds to PCIe Controller D, Function 1

Bit 19: Corresponds to PCIe Controller D, Function 2

Bit 20: Corresponds to PCIe Controller D, Function 3

Bit 21: Corresponds to PCIe Controller E, Function 0

Bit 22: Corresponds to PCIe Controller E, Function 1

Bit 23: Corresponds to PCIe Controller E, Function 2

Bit 24: Corresponds to PCIe Controller E, Function 3

Bit 25: Corresponds to DMI Controller

Bit 26: Corresponds to UFS Controller 2

Bit 27: Corresponds to PCIe Controller F, Function 0

Bit 28: Corresponds to PCIe Controller F, Function 1

Bit 29: Corresponds to PCIe Controller F, Function 2

Bit 30: Corresponds to PCIe Controller F, Function 3

Bit 31: Corresponds to GBETSN Controller

This field is going to be used in conjunction with MSPDRTReq and MSPDRTRAck fields above. If ASL code intends to over-ride HW decisions, it will set the corresponding bit for a controller/function to 1 in ASLOR and use MSPDRTReq bits to power-up/power-down SPD.